HP and IBM have been able to get very close to Alpha performance with much lower clocked chips several times already. Give or take the same process they can never achieve the same clock rates as Alpha though, because Alpha is much simpler. They get their performance from being sophisticated arhictecturally, whereas Alpha is classical barebones RISC. All this tells me that Alpha is going to crash and burn, no matter how much the first iteration of I-64 sucks. You can only raise the clock frequency that much...
Period. End of story. They see too many similar ideas. They are supposed to operate under code of conduct similar to lawyers (who also won't sign NDAs)
Still? Back in my time (1-2 years ago) upper division classes were full because of undeclared hopefuls trying to boost their tech GPA. The way things work in Berkeley that you can get into CS program two ways. You either apply to School of Engineering as EECS major right out of school or you can apply to Letters & Science as undeclared major and then declare CS. The second way makes it easier to get into the school, but you need to get something like 3.5 in technical subjects the first year and getting harder every year. Anyway, I thought the new rules don't allow undeclared's in upper division CS anymore? God, I am really happy that I don't have to get in now. It was way easier back in 94 when I started.
I thought for a sec they will be talking about how you have the right to shift your stuff from time domain to frequency domain (video part of MPEG uses FFTs) Heh.
Much higher coffeine concentration is also true of the "Energy Drinks", eq Red Bull. BTW the original Austrian Red Bull can says "Do not mix with alcohol" in small print. (Everybody does of course) I think this is due to some amino acid that improves alcohol absorbtion into blood.
The hitachis are vector CPUs. You don't have much use for them, but they sure do run optimized linear alrebra codes fast. Most other machines on the list use commodity CPUs. Cray used to have a bunch of vector CPUs in MPP configuration, but now they just use Alphas. Doing a separate CPU line for supercomputers is just too expensive. Let's hope the vector stuff is gonna make a comeback in next generation "multimedia" instructions or something like that.
Trying to represent ones and zeroes by switching voltage levels like in semiconductor transistors is not the best way to utilize superconductors. Take a look RSFQ logic:
Stealh planes are invisible to nacked eye because they only let them fly at night. Also stealth can be seen on a meter wave radar. That makes it not worth it.
Actually, PNG is the internal image format used by MS Office. It is not widely advertised, but acknowleged. libpng (reference implementation is available in source) The only issue I have with it is that it relies heavily on FP hardware. A truly portable implementation should work on integer-only hardware.
build a NOW over Myrinet, just 1.2K per node. Myricom claims that on PCs, the bottleneck is PCI DMA performance. Network faster than internal bus. Not bad. www.myri.com
This is not about the CPU
on
R12K Debuts
·
· Score: 1
This is not a limitation of any specific CPU, but rather of SMP architecture. How many CPU do you want to hang out on a single chunk of memory? The ASCI machine with several thousands MIPS chips was an MPP setup. Sun Enterprise with 64 CPUs uses a crossbar to memory and god knows what other tricks that have nothing to do with CPU itself. You pay dearly for stuff like this...
This is the MIPS swan song. As far as I know there is no next generation MIPS CPU in the pipeline. The 'Beast' project and the next one after that are dead. Or is this the 'Beast'? Doesn't look like it. Beast had a target clock of around 666Mhz. SGI is probably moving everything to Merced. I think the E2k looks interesting to peolple like SGI. CT never posted my translations of the Russian articles, so let me give you a recap. E2K uses a binary recompilator. Something like DEC's FX32!, but with hardware support. Apparently their recompiler is easily retargetable. They now can compile x86 and SPARC to E2K and run on the simulator. They plan to add Merced once the ISA is fully disclosed. They claim to have booted Windoze on a SPARC and ran Flight simulator, which supposedly won Babayan a bet with Mr. Ross (Ross Technologies, creators of HyperSPARC) They can probably add MIPS and any other "legacy" architecture relatively easily...
MIPS is royally screwed now. I mean, what is it? If you sell it as a high performance "compiler-friendly" architecture, there is Alpha. They will be hard-pressed to consistently outperfrom Alpha. An embedded architecture? Well, a lot of people use it. I suppose that's because they used Patterson/Hennesy books in their CPU design class at school. IMHO, MIPS is horribly miscast as an embedded architecture. Because it is so streamline, the code density is horrible.
Alpha is a canonical RISC machine, more so than SPARC or PPC. The only simpler instruction set out there is MIPS. This means Alpha will be hurt even more by the problems that are plaguing all high-end RISC designs now. It is becoming the very antithesis of itself. Very very complex. It's time to move beyond RISC.
Slashdot Mirror
Some of my favborites too, but are there good english translations? If you read Russian, there are texts available online...
HP and IBM have been able to get very close to Alpha performance with much lower clocked chips several times already. Give or take the same process they can never achieve the same clock rates as Alpha though, because Alpha is much simpler. They get their performance from being sophisticated arhictecturally, whereas Alpha is classical barebones RISC. All this tells me that Alpha is going to crash and burn, no matter how much the first iteration of I-64 sucks. You can only raise the clock frequency that much...
Period. End of story. They see too many similar ideas. They are supposed to operate under code of conduct similar to lawyers (who also won't sign NDAs)
is now with Cohera (www.cohera.com) They are doing "federated" databases
Still? Back in my time (1-2 years ago) upper division classes were full because of undeclared hopefuls trying to boost their tech GPA. The way things work in Berkeley that you can get into CS program two ways. You either apply to School of Engineering as EECS major right out of school or you can apply to Letters & Science as undeclared major and then declare CS. The second way makes it easier to get into the school, but you need to get something like 3.5 in technical subjects the first year and getting harder every year. Anyway, I thought the new rules don't allow undeclared's in upper division CS anymore? God, I am really happy that I don't have to get in now. It was way easier back in 94 when I started.
I think if Feds want to see if there is really
200K shortage, they should let H-1B switch job
as easily as it is for residents/citizens.
I think both sides have a point. Yes, there is
a huge shortage and yes, H-1Bs are indentured
slaves.
I thought for a sec they will be talking about how
you have the right to shift your stuff from time
domain to frequency domain (video part of MPEG
uses FFTs) Heh.
Much higher coffeine concentration is also true
of the "Energy Drinks", eq Red Bull. BTW the
original Austrian Red Bull can says "Do not mix
with alcohol" in small print. (Everybody does of
course) I think this is due to some amino acid
that improves alcohol absorbtion into blood.
The hitachis are vector CPUs. You don't have much
use for them, but they sure do run optimized linear alrebra codes fast. Most other machines
on the list use commodity CPUs. Cray used to
have a bunch of vector CPUs in MPP configuration,
but now they just use Alphas. Doing a separate
CPU line for supercomputers is just too expensive.
Let's hope the vector stuff is gonna make a
comeback in next generation "multimedia" instructions or something like that.
Trying to represent ones and zeroes by switching
voltage levels like in semiconductor transistors
is not the best way to utilize superconductors.
Take a look RSFQ logic:
http://pavel.physics.sunysb.edu/RSFQ/RSFQ.html
They represent bits with quanta of magnetic flux.
Sucks as a cluster interconnect. You can do factor
of 100 better with something like Myrinet unstead
of Gigabit Ether for about the same money.
Stealh planes are invisible to nacked eye because
they only let them fly at night.
Also stealth can be seen on a meter wave radar.
That makes it not worth it.
Actually, even the language is the same. Serbs,
Croats and Bosnians all speak Serbo-Croatian.
DICE is the best. in my expirience. The only
job board that actually does something for us
contractors. I also love the area code search
function.
Actually, PNG is the internal image format used
by MS Office. It is not widely advertised, but
acknowleged. libpng (reference implementation
is available in source) The only issue I have
with it is that it relies heavily on FP hardware.
A truly portable implementation should work on
integer-only hardware.
Of course. Myrinet will set you back $1.2-1.5K
per node in networking gear.
well, its not that bad.
build a NOW over Myrinet, just 1.2K per node.
Myricom claims that on PCs, the bottleneck is
PCI DMA performance. Network faster than
internal bus. Not bad. www.myri.com
This is not a limitation of any specific CPU,
but rather of SMP architecture. How many CPU
do you want to hang out on a single chunk of
memory? The ASCI machine with several thousands
MIPS chips was an MPP setup. Sun Enterprise
with 64 CPUs uses a crossbar to memory and god
knows what other tricks that have nothing to do
with CPU itself. You pay dearly for stuff like
this...
This is the MIPS swan song. As far as I know
there is no next generation MIPS CPU in the
pipeline. The 'Beast' project and the next one
after that are dead. Or is this the 'Beast'?
Doesn't look like it. Beast had a target clock of
around 666Mhz. SGI is probably moving everything to Merced.
I think the E2k looks interesting to peolple like SGI. CT never posted my translations of the Russian articles, so let me give you a recap. E2K uses a binary recompilator. Something like DEC's FX32!, but with hardware support. Apparently their
recompiler is easily retargetable. They now
can compile x86 and SPARC to E2K and run on the
simulator. They plan to add Merced once the ISA
is fully disclosed. They claim to have booted Windoze on a SPARC and ran Flight simulator, which
supposedly won Babayan a bet with Mr. Ross
(Ross Technologies, creators of HyperSPARC) They can probably add MIPS and any other "legacy" architecture relatively easily...
MIPS is royally screwed now. I mean, what is it?
If you sell it as a high performance
"compiler-friendly" architecture, there is Alpha.
They will be hard-pressed to consistently outperfrom Alpha. An embedded architecture? Well,
a lot of people use it. I suppose that's because
they used Patterson/Hennesy books in their
CPU design class at school. IMHO, MIPS is horribly
miscast as an embedded architecture. Because it
is so streamline, the code density is horrible.
The question should be, why won't Apple give out
the sources?
Alpha is a canonical RISC machine, more so than
SPARC or PPC. The only simpler instruction set
out there is MIPS. This means Alpha will be hurt
even more by the problems that are plaguing all
high-end RISC designs now. It is becoming the
very antithesis of itself. Very very complex.
It's time to move beyond RISC.