Early childhood is a development stage like any other - don't hold on to it and symbols of it like trophies. Learn to forget. Savor the happy moments for what they are - but don't fetishise them. Your memory will remember what is appropriate. Maintaining the image of a helpless infant in your mind will not make a better parent in the long term - the opposite, more like it. Take care and give them security. But make well fucking sure that they know that they know they are their own persons, with their own right of opinion, by the age of twelve. Over and out. Oh, and just for the record - XFS+LVM on a RAID5 of RAID1ed drives with staggered spin-up with some nice ARM board in micro-ATX form factor ought to do the trick, for what you are thinking. Zenwalk or a tweaked Fedora install image would make life easier.
Shared memory access speed is still a mainframe stronghold. Though the logical structuring of the channel procs is... more logical, as well. PCIe latency for issuing IO commands cuts into IOPS, throughput is how much you put in, no matter where the die is, and hell, there are just a few standard protocols - integrate in the damn CPU already - or the motherboard. Oh, and FC is expensive, brittle, and doesn't give you anything high-density Ethernet+MPLS won't. IB is nice - but could be replaced with a (large) handful of IEEE1394 links (possibly with an iWARP implementation), in most cases, IMHO. Well, it does have a lead on latency... Otherwise, I agree completely. Mainframes were never priced competitively.
I think Intel will be looking around for that Transmeta IP any day, now. And getting into reverse engineering FX!32. Maybe call up their buddy IBM for some source code of a certain bought out z/Arch emulating start-up that Apple licensed at a certain moment in time.
Not to mention having multiple unprivileged addressing modes - non-orthogonal, almost any number of address spaces - in a single process. In user mode. Oh, and these are the ones in 64-bit mode - you can mix and match with the two older modes - you even have special instructions for it. 5 or 6 instruction formats. Microcoded or hardware implemented or just plain missing instructions (some). And... You get the idea.
Decoded instructions (micro-ops) are created by the hardware decoder. Microcode is programmable - does nearly the same thing, handles complex instructions well. A procedure ROM is a whole other thing.
Actually, it is. It is also about orthogonal semantics - no implicit registers, no perverse addressing modes, not to deep a state tree when executing any single instruction (mostly means keeping memory accesses capped - leads to very neat pipelinening.
Separation of interface and presentation surfaces means having a cursor. I think tablets are a fad because it's one layer of indirection too many, though standard disclaimers apply.
Oh, please - Commodore 128 equivalent laptops with monochrome displays and good documentation would be a much better start - hell, put in different ISAs - 6502, m68k, Z81, B5000, ARMv1, S/360.
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Early childhood is a development stage like any other - don't hold on to it and symbols of it like trophies. Learn to forget. Savor the happy moments for what they are - but don't fetishise them. Your memory will remember what is appropriate. Maintaining the image of a helpless infant in your mind will not make a better parent in the long term - the opposite, more like it. Take care and give them security. But make well fucking sure that they know that they know they are their own persons, with their own right of opinion, by the age of twelve. Over and out. Oh, and just for the record - XFS+LVM on a RAID5 of RAID1ed drives with staggered spin-up with some nice ARM board in micro-ATX form factor ought to do the trick, for what you are thinking. Zenwalk or a tweaked Fedora install image would make life easier.
Shared memory access speed is still a mainframe stronghold. Though the logical structuring of the channel procs is... more logical, as well. PCIe latency for issuing IO commands cuts into IOPS, throughput is how much you put in, no matter where the die is, and hell, there are just a few standard protocols - integrate in the damn CPU already - or the motherboard. Oh, and FC is expensive, brittle, and doesn't give you anything high-density Ethernet+MPLS won't. IB is nice - but could be replaced with a (large) handful of IEEE1394 links (possibly with an iWARP implementation), in most cases, IMHO. Well, it does have a lead on latency... Otherwise, I agree completely. Mainframes were never priced competitively.
I think Intel will be looking around for that Transmeta IP any day, now. And getting into reverse engineering FX!32. Maybe call up their buddy IBM for some source code of a certain bought out z/Arch emulating start-up that Apple licensed at a certain moment in time.
Not to mention having multiple unprivileged addressing modes - non-orthogonal, almost any number of address spaces - in a single process. In user mode. Oh, and these are the ones in 64-bit mode - you can mix and match with the two older modes - you even have special instructions for it. 5 or 6 instruction formats. Microcoded or hardware implemented or just plain missing instructions (some). And... You get the idea.
VLE does not a CISC make - check out PPC Embedded profile.
Decoded instructions (micro-ops) are created by the hardware decoder. Microcode is programmable - does nearly the same thing, handles complex instructions well. A procedure ROM is a whole other thing.
Actually, it is. It is also about orthogonal semantics - no implicit registers, no perverse addressing modes, not to deep a state tree when executing any single instruction (mostly means keeping memory accesses capped - leads to very neat pipelinening.
Isn't that bitshifitng?
IANAPsychiatrist, but touch ought to lead to an oxytocin rush.
Is it? Frankly I'm OK with this vampire going after Buffy. Let the gov and the fat cats fight it out. Here's for hoping they kill each other.
Sounds like a job for a single android app.
What kind of trouble did you run in to?
CPU cache is a bottleneck.
Separation of interface and presentation surfaces means having a cursor. I think tablets are a fad because it's one layer of indirection too many, though standard disclaimers apply.
Make and model, if you would be so kind?
What does Java provide?
Qt can do that for you. Though I'm not sure of the hardware.
You just reinvented the artificial heart.
It's called fish (friendly interactive shell). It's in the repos.
The GPP is getting at it from the wrong angle - these kids will grow up using Apple - they are the next generation fanbois - God help us all.
Oh, please - Commodore 128 equivalent laptops with monochrome displays and good documentation would be a much better start - hell, put in different ISAs - 6502, m68k, Z81, B5000, ARMv1, S/360.
Not that I'm a fanboi, but [[citation needed]]. I'm really curious.
Mod parent up +1 Realist
AdBlock Plus. Geek card please.
Mod parent up +1 Down To Earth.