SiLK which is used for microprocessor applications is not connected in any way to spider silk. The former is an acronymn for a resin (aromatic hydrocarbon) made by Dow Chemicals and used by IBM and other chip companies as an insulator between the multiple layers of wires on a chip. Silicon Low-K = SiLK
Metal gates have 4 main advantages in advanced CMOS transistors: (1) The gate resistance is reduced. This lowers the switching delay in some cases. Remember that the delay is proportional to the product of the resistance and capacitance (the 'RC' product).
(2) In polysilicon gates, the free carrier density is very high (1E20 carriers per cubic cm). Even so, under high electric fields that are needed to switch a transistor, there is a small depleted layer created right at the interface of the gate and the dielectric. This effectively acts as a capacitor in series with the dielectric and increases what is called the "effective oxide thickness". This is very bad, especially when process engineers are trying extremely hard to reduce the oxide thickness. At the scales we are at now, every Angstrom counts. In metal gates, the carrier density is 1000X higher. This makes it much harder to deplete and you regain the 4 angstroms. This means either higher performance with the same gate dielectric thickness, or you can get the same performance and increase the dielectric thickness by 4A, thereby reducing the gate tunneling leakage current (and hence power) by an order of magnitude. This is a big deal.
(3) Some high dielectric constant materials (that are candidates to replace silicon dioxide) are not very compatible with polysilicon. This could mean either thermodynamic instability or interfacial charge created that "pins" the workfunction (and affects the switching threshold voltage of the transistor)
(4) In fully-depleted silicon on insulator (FD-SOI, or "depleted substrate transistor" in Intel parlance) transistors, the threshold voltage comes out wrong when using doped polysilicon gates. It makes the transistor either too slow or too leaky. There is a desperate need for tuning the threshold voltage by using a different workfunction which can be found in some metal gates.
Of course, metal gates aren't without their problems. (the predecessors of today's transistors had metal gates - hence the 'M' in CMOS - Complementary METAL Oxide Semiconductor - which were replaced by polysilicon gates for processing ease.) Inability to be easily patterned, withstand high processing temperatures, reliability issues are just a few of them.
What happened to those? Are they being made but covered up by NDAs? Did they jump ahead too far, then had to go back to do more basic research on the properties of materials at that scale? Surely SOMEONE on Slashdot works at a materials lab and can clue me in.
A company called Zyvex plans to build such micro-scaled machines. Check out their website for details
Slashdot Mirror
SiLK which is used for microprocessor applications is not connected in any way to spider silk. The former is an acronymn for a resin
(aromatic hydrocarbon) made by Dow Chemicals and used by IBM and other chip companies as an insulator between the multiple layers of wires on a chip. Silicon Low-K = SiLK
Metal gates have 4 main advantages in advanced CMOS transistors:
(1) The gate resistance is reduced. This lowers the switching delay in some cases. Remember that the delay is proportional to the product of the resistance and capacitance (the 'RC' product).
(2) In polysilicon gates, the free carrier density is very high (1E20 carriers per cubic cm). Even so, under high electric fields that are needed to switch a transistor, there is a small depleted layer created right at the interface of the gate and the dielectric. This effectively acts as a capacitor in series with the dielectric and increases what is called the "effective oxide thickness". This is very bad, especially when process engineers are trying extremely hard to reduce the oxide thickness. At the scales we are at now, every Angstrom counts. In metal gates, the carrier density is 1000X higher. This makes it much harder to deplete and you regain the 4 angstroms. This means either higher performance with the same gate dielectric thickness, or you can get the same performance and increase the dielectric thickness by 4A, thereby reducing the gate tunneling leakage current (and hence power) by an order of magnitude. This is a big deal.
(3) Some high dielectric constant materials (that are candidates to replace silicon dioxide) are not very compatible with polysilicon. This could mean either thermodynamic instability or interfacial charge created that "pins" the workfunction (and affects the switching threshold voltage of the transistor)
(4) In fully-depleted silicon on insulator (FD-SOI, or "depleted substrate transistor" in Intel parlance) transistors, the threshold voltage comes out wrong when using doped polysilicon gates. It makes the transistor either too slow or too leaky. There is a desperate need for tuning the threshold voltage by using a different workfunction which can be found in some metal gates.
Of course, metal gates aren't without their problems. (the predecessors of today's transistors had metal gates - hence the 'M' in CMOS - Complementary METAL Oxide Semiconductor - which were replaced by polysilicon gates for processing ease.) Inability to be easily patterned, withstand high processing temperatures, reliability issues are just a few of them.
A company called Zyvex plans to build such micro-scaled machines. Check out their website for details