The node is supposed to be the 22nm node and is only two shrinks away. This means the big companies are hiring R&D personal for that node right now, we are not talking about 2020.
I would not be worried about physics, but rather about economics. Currently many big companies are exiting process development and cutting edge manufacturing and start to rely on foundries. And we are talking top10 companies: Texas Instruments (inventor of the IC!), Sony, Infineon, Cypress, NXP (Philips), NEC (to some extend). The number of foundries supplying the most advanced manufacturing processes is much less than the number of companies quitting development - maybe 3 to 4.
Less parallelism in development means that there is less variety, which will lead to a slowdown. Also the funding for R&D at tool vendors will reduce as a direct consequence of having fewer people buying experimental tools. By the time the graphene transistor would be ready there may very well be just one or two companies being able to make use of it..
Science is hard and not sexy. There are also too few electrical engineers (not VHDL programmers), semiconductor scientists, material scientists, physicists and what not is needed to feed the entire information technology chain.
On the other hand - the other posts are probably right about the common misconception of computer science and programming.
The alternative would have been just to shrink the devices, gain less on performance and use circuit techniques to battle parasitic power consumption. That is what most companies in cost sensitive markets are going to do.
Actually I believe there are only two properties of diamond that are superior to silicon in respect to electronic application: Heat conductivity and band gap.
The disadvantages are numerous, starting with the very basic fact that there is no known n-type dopant for diamond.
AFAIR Intel presented some interesting technologies studies on SOI a couple of years ago.
Your wafer cost figures are off, but I will rather not comment due to lack of public sources. Still, in most parts of the semiconductor business 10% cost difference is not a wash but determines whether you make profit or not. It may work for a short while if you have a very high margin product (like a technologically superior CPU), but then you are suddenly in a price war...
I can tell you this is not FUD. If you follow the literature about this subject closely you will notice that there is no report about a metal usable for a pMOS transistosr. Many companies are not significantly ahead of that. I expect some pretty interesting publications later this year. But it still takes several years to get a new material into production. Intel has already made big strides in putting high-k into production while other companies may still be in the screening process. I believe they have a head start of at least one year, if not more. Note that IBM announced the usage of High-k for 2008, at least a year later than intel.
This is the first time since 1969 that a major modification to the MOSFET gate stack occured. In fact it is fairly major. I should remind you that this is a structure that is replicated around 1e19 times each year and is responsible for the biggest part of the 270 Billion US$ semiconductor market.
At least ten years of work in academia and industry and billions of dollars were poured into this. Intel is the first company to make the move and introduce high-k.
(Yes, there were a few minor modifications to the SiO2/Poly stack in between: Plasma nitridation and numerous improvements on SiO2 growth)
I think while being smartassy and all you completely forgot that the atomic radius is not equivalent to lattice spacing in crystals. Your numbers are way off.
Lets assume paper resolution is limited to 600dpi. The color fidelity that can be recognized accurately is probably less than 18bit.
So, somehow we end up with 600*600*18*8*11=570240000bits which is 68 megabytes. Subtracting 50% for error correction (probably still way too conservative) we end up with 35 megabytes of usable data.
Not impressive anymore? Well, add to that that an extremely expensive scanner is required to read the data. Suddenly USB sticks look like a much cheaper medium...
Sorry, I dont see why this is a story. The technical difficulty of this is something like "my first microcontroller project" from "toying with electronics 101". The implementation is not even that interesting. (Multiplexing anyone?). The novelty is almost zero (giant LED display.. uhhh). Yes, it is at this geek university, but that is the only real point about this story i can see.
Collossus is not a computer, it was not freely programmable. It was merely able to do pattern matching with a couple of LFSRs. This is still miles from a turing complete machine.
This is not new - this is known as "susbtrate transfer process" and has been practiced for year. One company doing very advanced work in this is Philips:
Slashdot Mirror
But we get a much more important date before Pi day: 13-3-7 -> 1337 -> LEET DAY!!
IBM,AMD and IBM,Chartered are part of a development alliance so their strategies are pretty similar. You forgot UMC.
The node is supposed to be the 22nm node and is only two shrinks away. This means the big companies are hiring R&D personal for that node right now, we are not talking about 2020.
I would not be worried about physics, but rather about economics. Currently many big companies are exiting process development and cutting edge manufacturing and start to rely on foundries. And we are talking top10 companies: Texas Instruments (inventor of the IC!), Sony, Infineon, Cypress, NXP (Philips), NEC (to some extend). The number of foundries supplying the most advanced manufacturing processes is much less than the number of companies quitting development - maybe 3 to 4.
Less parallelism in development means that there is less variety, which will lead to a slowdown. Also the funding for R&D at tool vendors will reduce as a direct consequence of having fewer people buying experimental tools. By the time the graphene transistor would be ready there may very well be just one or two companies being able to make use of it..
They deserve a Golden Hourglass award for 'extreme waste of time.' What obscure hardware configurations have you managed to get Windows running on?"
./.. or any weblog.
They do? In fact this is still slightly more intellectually stimulating than reading and posting on
Maybe when some other country takes the initiative and produces something useful the U.S. will copy.
Already happening. There have been several cases of industry espionage from the US on european wind turbine makers.
Science is hard and not sexy. There are also too few electrical engineers (not VHDL programmers), semiconductor scientists, material scientists, physicists and what not is needed to feed the entire information technology chain.
On the other hand - the other posts are probably right about the common misconception of computer science and programming.
The alternative would have been just to shrink the devices, gain less on performance and use circuit techniques to battle parasitic power consumption. That is what most companies in cost sensitive markets are going to do.
Nice, I was not aware of the later work. It is still a far way towards proper junctions.
Actually I believe there are only two properties of diamond that are superior to silicon in respect to electronic application: Heat conductivity and band gap.
The disadvantages are numerous, starting with the very basic fact that there is no known n-type dopant for diamond.
AFAIR Intel presented some interesting technologies studies on SOI a couple of years ago.
Your wafer cost figures are off, but I will rather not comment due to lack of public sources. Still, in most parts of the semiconductor business 10% cost difference is not a wash but determines whether you make profit or not. It may work for a short while if you have a very high margin product (like a technologically superior CPU), but then you are suddenly in a price war...
That is not true. There will be a number of companies doing 45nm without high-k and metal gates.
This article offers some hints:
http://www.fabtech.org/content/view/2079
also: HOT and SOI are quite expensive, it saves a lot of money (at least now) to engineer around those solutions.
I can tell you this is not FUD. If you follow the literature about this subject closely you will notice that there is no report about a metal usable for a pMOS transistosr. Many companies are not significantly ahead of that. I expect some pretty interesting publications later this year. But it still takes several years to get a new material into production. Intel has already made big strides in putting high-k into production while other companies may still be in the screening process. I believe they have a head start of at least one year, if not more. Note that IBM announced the usage of High-k for 2008, at least a year later than intel.
That is not entirely correct. Intel had basically maxed out SiON previously, I doubt they could have gained that much in performance without high-k.
This is the first time since 1969 that a major modification to the MOSFET gate stack occured. In fact it is fairly major. I should remind you that this is a structure that is replicated around 1e19 times each year and is responsible for the biggest part of the 270 Billion US$ semiconductor market.
At least ten years of work in academia and industry and billions of dollars were poured into this. Intel is the first company to make the move and introduce high-k.
(Yes, there were a few minor modifications to the SiO2/Poly stack in between: Plasma nitridation and numerous improvements on SiO2 growth)
yay.. useless imperial units used for meaningful physical calculations. I hope this is a posting from the past.
I think while being smartassy and all you completely forgot that the atomic radius is not equivalent to lattice spacing in crystals.
Your numbers are way off.
Various stuff I build while having to much free time at university.
(Or taking too much free time.. well..)
- Entire 4bit CPU out of TTL parts (~60 ics)
- Complete 32bit Computer on FPGA
- Various semiconductor solar cells. I wish I could find an apartment where they'd let me keep my chem lab.. na..
Yeah, and now lets assume realistic numbers.
Lets assume paper resolution is limited to 600dpi. The color fidelity that can be recognized accurately is probably less than 18bit.
So, somehow we end up with 600*600*18*8*11=570240000bits which is 68 megabytes. Subtracting 50% for error correction (probably still way too conservative) we end up with 35 megabytes of usable data.
Not impressive anymore? Well, add to that that an extremely expensive scanner is required to read the data.
Suddenly USB sticks look like a much cheaper medium...
Sorry, I dont see why this is a story. The technical difficulty of this is something like "my first microcontroller project" from "toying with electronics 101". The implementation is not even that interesting. (Multiplexing anyone?). The novelty is almost zero (giant LED display.. uhhh). Yes, it is at this geek university, but that is the only real point about this story i can see.
Collossus is not a computer, it was not freely programmable. It was merely able to do pattern matching with a couple of LFSRs. This is still miles from a turing complete machine.
That is opposed to the continuous alpha testing that all users of open source software do?
This is not new - this is known as "susbtrate transfer process" and has been practiced for year. One company doing very advanced work in this is Philips:
i on/hf/ectm013.pdfi on/hf/111568631.pdf
First two paper hits I found in google:
http://retina.et.tudelft.nl/data/artwork/publicat
http://retina.et.tudelft.nl/data/artwork/publicat
Many companies are also working on substrate transfer processes to build silicon wafers with selective crystal orientation. Among them IBM and Soitec.