Thanks for posting this, I've been confused on the cache implementation for Duron, and Thunderbird for a while thinking the standard was going to be 256k L2 for Duron, and 512k L2 for T-bird. But I had no idea of the cache being unique from each other. At least this way L2 isnt L1's bitch so to speak. Now I hope they dont go blocking out SMP for Durons...........hopefully.
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Thanks for posting this, I've been confused on the cache implementation for Duron, and Thunderbird for a while thinking the standard was going to be 256k L2 for Duron, and 512k L2 for T-bird. But I had no idea of the cache being unique from each other. At least this way L2 isnt L1's bitch so to speak. Now I hope they dont go blocking out SMP for Durons...........hopefully.