Sun will somehow finish a significantly more complex processor when they give up on this one?
Uhh, Niagara is a MUCH simpler processor than the UltraSparc V! Where the US V was supposed to be a very complicated, high-end core, Niagara is just a whole bunch of fairly simple cores glued together.
I'm sure someone on/. has said that many times over, but it's not at all the case.
For those who are too lazy to read the article, Sun is NOT killing off the SPARC line, they are NOT discontinuing all their CPU production and they are NOT switching everything to AMD64 chips.
What Sun is doing is finally putting an end to their rather unsuccessful attempts to produce a single-threaded raw number crunching chip. Sun hasn't been successful at this for some time now (certainly since at least the UltraSparc II and probably for a while before then) and the UltraSparc V was just going to be another failure in this regard. No one buys Sun's for their raw number crunching performance anyway (since they stink in this regard), so this is really a pretty bright move by Sun. Really it's something they should have done a while ago.
The plan going forward is for Sun to work to their strengths. Their CPU division will produce highly multithreaded chips that are designed for server work, ie the sort of stuff that people buy Suns for in the first place. Their workstation line will be replaced by AMD64 systems since EVERYONE is moving their workstation line to x86 anyway. The only thing holding people to Sun workstations (and IBM or SGI workstations as well) was the lack of 64-bit capabilities on x86 chips, but that restriction is no more.
Sun will still need some SPARC workstation products for a while going forward to support customers with legacy Solaris software that can't easily be upgraded though. If they are smart, what Sun will do is buy some SPARC64-V chips from Fujitsu. This gives Sun faster chips for much lower cost then developping their own.
Did you ever wonder why no one sells x86 servers with more than 8 CPUs
You mean servers like this or IBM's plans detailed here? x86 servers with more than 8 processors definitely do exist, even if they are somewhat rare.
Well, one reason is the x86 architecture doesn't scale with a crap in a multiple-CPU box
That has very little to do with the processor itself and MUCH more to do with the supporting components. One problem that x86 chips have traditionally had is the lack of a high-bandwidth and low-latency bus for I/O, but with the Opteron that potential weakness is gone. Given decent supporting hardware AND software the Opteron can (and does) scale VERY well.
What they are doing is simply a change in strategy, and the right change IMO. Sun hasn't been competitive in raw number crunching and single-threaded performance for quite some time and the UltraSparc V wasn't going to be enough to save them. However they were spending a LOT of money to not be very successful. Sun had the second largest CPU development team in the world after Intel, yet companies like AMD and Fujitsu were producing faster (single-threaded) processors for much lower costs. In other words, it just wasn't working for Sun.
What IS working for Sun is multithreading performance. The UltraSparc IV now gives them up to 144 processor cores in a single image system, only SGI is doing more. They combine that really good I/O and solid software support and you have a pretty good solution for a high-end servers. It's not a very good choice for supercomputer-type applications (that's what SGI is after), nor is it very good for workstations, but Sun was getting killed in those markets anyway.
This announcement also ties back into the deal with AMD. While Sun hasn't been doing a very good job for workstation and number-crunching chips, AMD IS doing great here. The Opteron is a great chip for these sorts of tasks and fills in many of the wholes that could potentially be left by the death of the US V. Now all Sun needs is to get the software support up to par for x86-86 Solaris (as well as Linux and maybe even Windows) and they'll be in a reasonable position.
In short, in my mind this is the right decision by Sun. The only thing that I think is bad about it is that they waited so long. IMO they should have killed of the US V a couple years ago!
The Intel i875 does NOT include Gigabit ethernet in the north bridge (aka Memory Communications Hub, or MCH). What it has is a separate bus (CSA or Communication Streaming Architecture) that is designed to directly connect to a discrete gigabit ethernet controller. To the best of my knowledge, Intel is the only company producing those disctere CSA ethernet chips.
The only new thing about the RAID support is that this works with both SATA and Parallel ATAI drives together. Previous solutions could only use either SATA or parallel ATA in any given array. Not a huge advance, but a nice little extra.
Yeah, much better to have two or three chips in a machine where if any one of them die than the whole systme is useless! That's what we've got now, where most chipsets come with 2 or 3 discrete chips, and you better believe that if any one of them dies then your system won't boot.
nVidia didn't really have a choice in the matter, AMD yanked the memory controller on-die, making it basically impossible to design a board in the same way that they had designed the nForce and nForce2 IGPs.
Now, don't get me wrong, I think the integrated memory controller is a GREAT idea and definitely the way to go, but it does cause some problems for integrated video, particularly on the current Athlon64 chips with only a 64-bit 400MT/s memory bus.
Fortunately there is a potential solution, and it should result in even better integrated video when it's economically feasible. The solution is to hang the video memory right off the motherboard chipset. SiS is doing this now with their SiS760 chipset. In fact, they ahve a rather nifty design where you can either use the memory connected to the processor main memory controller (shitty performance but super-cheap), hang memory off the motherboard chipset (much better performance but more expenisve) or even a combination of the two (not much of an advantage, but it does allow you to put a small amount of fast memory on the motherboard but still have access to other memory when needed).
I suspect that nVidia will come up with a design like this in the future. If they really want to push things forward they might even make a chipset with eDRAM integrated right onto the die. This would give them TONS of bandwidth, though it would restrict them to a relatively small amount of memory on chip.
The Intel i875 chipsets integrated NIC is only a 10/100 chip. The Communication Streaming Architecture (CSA) bus is used to directly connect the chipset to an add-in NIC chip, by-passing any bandwidth and latency hit you might take if going through a shared bus.
The difference is perhaps a bit academic though, since Intel sells the NIC chip to you plug onto the far end of the CSA bus, and I wouldn't be at all surprised if they have some sort of deal where you can buy an i875 chipset together with an Intel 82547 CSA ethernet controller. As far as I know, Intel is the only company producing CSA ethernet controllers, so it's kind of like getting it as one "chipset".
So you think that somehow having all these features implemented by different companies and trying to bodge all their drivers together will INCREASE stability?
Compare a motherboard chipset from nVidia, a NIC chip from 3Com, a graphics chip from ATI, an IDE controller from Promise and a sound card from Creative Labs to getting ALL of those features from nVidia. Which situation do you think is more likely to be tested together and less likely to cause interoperability problems?
If I can get GOOD quality components integrated onto the motherboard and pay next to nothing for them I am VERY happy. On my old system I had tons of problems getting my Creative Labs sound card to work with my VIA motherboard chipset, and my no-name Tulip chipset NIC didn't want to play at all with my nVidia video card.
Now I've got an nVidia chipset board with integrated sound, NIC and video and it works VERY well. I've had MUCH better stability with this integrated solution than with discrete chips.
The fire at the resin plant was a total smoke-screen, it had a negligible effect on production or costs.
The DRAM shortage that occured at that time had a LOT of reasons associated with it, but the short version is that it all boiled down to supply and demand. Despite having a large chunk of the international DRAM market, none of the companies were making any money because prices were so low. So, to try and fix this, they decided to constrain the supply a bit. Supply goes down while demand was going up at the same time. End result? Huge increase in price. The resin plant fire was just a nice scapegoat to point blame at.
The Koreans broke the monopoly because they didn't worry about making any money. They figured that they would get marketshare first while their government propped the company up and then eventually start making money several years down the road. This worked fairly well for Samsung, who are now the worlds #1 memory manufacturer. It didn't work at all for LG Semiconductor or Hyundai Semi (now groupped together as Hynix). Both of those companies lost billions of dollars and they continue to lose billions of dollars, though the Korean government still props them up. Fairly recently they were found to violate some trade restrictions because of these government handouts and now need to pay fairly hefty levies to sell their products in the US.
In any case, while this is all slightly off-topic for the article, it is something that is going to be rather important to remember in the next 6 months or so. Several memory companies have announced plans to reduce production while at the same time advising that they will be unable to meet demand. In other words, they're doing it all over again, restricting supply in order to boost revenue (and maybe even make a profit, since most memory companies are not at all profitable). Expect memory prices to rise fairly significantly throughout the course of this year and don't be at all surprised if an earthquake in Taiwan or a resin plant fire in Japan is blamed for the hike.
No, the G5 doesn't have a 1GHz HT bus... or ANY Hypertransport bus for that matter.
It has a 1.0GT/s Elastic I/O bus, dual 32-bit wide unidrectional point to point connection used for both memory and other I/O.
This is quite inferior to the Opterons current 128-bit wide 400MT/s memory bus + 3 hypertransport buses for other I/O, each running at 1600MT/s and 16-bits in either direction.
The PowerPC 970 (aka G5 in Apple-speak) is a prefectly good chip, but when it comes to I/O it is very much outclassed by the Opteron. On the upside though, it has the Xeon beat cold, but that's not saying much. The crappy bus is a known shortcoming if the Xeon and the reason why those chips suck bilge water in 4 processor setups.
First point, Apple had exactly ZERO to do with developping Hypertransport. Nothing, nodda, zippo, zilch! Hypertransport is primarily an AMD developped technology with a little bit of help from the now defunct API (Alpha Processor Inc.). Apple may be part of the Hypertransport Consortium, but so are about 90 other companies that had nothing to dow ith the development of Hypertransport.
Second point, the PowerPC 970 does NOT use Hypertransport as it's bus! Hypertransport in the PowerMac G5 is ONLY used as an interconnect between the memory and processor controller and the other two I/O chips (at least one of which is actually an AMD chip).
The PPC 970 uses the Elastic I/O bus, designed and developped by none other than IBM. This is a dual 32-bit wide unidirectional point-to-point bus running at up to 1.0GT/s. The bus isn't all that well documented, so I'm not sure if it's a true 1.0GHz bus or a 500MHz DDR bus or a 250MHz QDR bus. I would guess it's 250MHz QDR, though the difference is somewhat accademic. Either way, the bus provides for up to 4.0GB/s of bandwidth in either direction and since it is point-to-point connection, the bus is not shared on dual-processor systems.
In the end, this bus is actually a lot like what AMD used to use on their AthlonXP and AthlonMP line. The only differences are that the PPC 970 bus runs at a higher effective data rate and it is a pair of 32-bit unidirectional buses rather than the single 64-bit bi-directional bus on the AthlonXP.
For the Intel side of things you get a 400MT/s (100MHz QDR) to 800MT/s (200MHz QDR) 64-bit wide bi-directional bus. Current Xeons top out at 533MT/s (133MHz QDR). Unlike the AthlonMP and PowerPC 970 bus, Intel uses a shared bus. This is why the Xeon doesn't scale too well going from one to two processors and scales pretty horribly when going from two to four processors (beyond 4 CPUs you need separate buses, crossbars and all sorts of other fancy things beyond the scope of this discussion). The next generation of Xeon, to be released anywhere between 1 and 9 months from now (depending on what source your look at) will go up to the same 800MT/s bus that the desktop P4s use, that should provide a fairly decent boost in performance for multiprocessor Xeon systems. That will give the Xeon up to 6.4GB/s of bandwidth (either upstream or downstream, but not at the same time).
Of course, when it comes to the absolute beast of moving data around for commodity hardware, you have to look to the Opteron. While the G5 may easily have the Xeon beat in this regard, the Opteron stomps over both of them quite handily.
First and foremost, the Opteron changes all the rules by moving the memory controller on-die. On the PPC 970 and Intel P4/Xeon the memory controller hangs off the memory and processor controller chip (often called a "Northbridge", a name that dates back to early PCI days). This means that they are sharing one bus for both their memory tranfic and general purpose I/O. On the Opteron the two buses are separate. It has a 128-bit wide, 400MT/s (6.4GB/s) memory bus AND not one but *THREE* 1600MT/s dual 16-bit unidirectional Hypertransport connections for all other I/O. That's 3.2GB/s in either direction for each of the three HT links. Plus, since it's a NUMA architecture, in multiprocessor systems this bandwidth adds together rather than being shared.
What's perahps even more important than the raw bandwidth advantage the Opteron has over other setups is the latency advantage. Since everything is integrated onto the processor it significantly reduces the latency for I/O. In many applications latency is actually more important than raw bandwidth.
Long story short, don't look at just the clock speeds (or even the effective clock speeds that the marketing people like to toss around), there's a lot more too it than that. All three of these chips (PowerPC 970, Opteron and Xeon) have various advantages and disadvantages, but when it comes to I/O, the Opteron is far and away the leader of
Given Elbrus' history of delivering products, my guess is that this won't actually ship for a good 3-5 years.
I'd MUCH rather use Intel's XScale chip, that also runs at 500MHz, consumes only 500mW and also runs Linux and Windows (WinCE and Windows Mobile at least). Ohh, and it's shipping now, not 3-5 years from now.
There are plenty of other neat chips in similar power consumption ranges as well. IBM makes some PowerPC chips to compete, PMC Sierra has some MIPS chips and about 50 companies make fast but low powered ARM chips. There have even been a few other companies making low-power SPARC chips before, though they most have died out due to lack of market. I somehow doubt that Elbrus will fare any better.
Someone could probably double processor speed every 12 month instead of 18
Ironically enough, "Moore's Law" really DID specify a time span of 12 months! Of course that 12 month doubling thing didn't hold for very long, so the "law" was modified to 18 months and more recently to "about 18 to 24 months". Not really much of a law.
It's perhaps also important to point out that Moore never said anything about computing efficieny, but rather the number of transistors that you could put on one chip at any given price point. For example, Intel's new Prescott P4 processor isn't really any faster than the Northwood P4 processor that proceeded it, yet it has more than twice as many transistors. Moore's observation is holding true with this chip, transistor count did go up exponentially, however processor performance has not going up along with it.
Ok, I know complaining about unoptimized software is the popular thing to do on/., but honestly, why both optimizing software for fast processing?
Think of it, these days at least 99% of the biggest bottleneck in a computer system by a LONG margin is situated on the far side of the keyboard. You can optimize Word all to hell, make it process all my commands blazingly fast and yet it probably still won't manage to shave even 1 second off the amount of time it takes me to write a technical report.
Really what we need is software with GOOD functionality, not heavily optimized software. Programs with very efficient and usuable UIs will beat out software heavily optimized for fast executation but with a poor UI any day.
PowerPC chips are most definitely used in the embedded market! What the heck do you think powers Cisco routers? Or for that matter, the hardware diagnostics on Sun's Opteron-based V20z server? Hell, those two rovers doing their thing on Mars are using embedded PowerPC processors.
IBM's 4xx line of PowerPC chips are very much targetted at the embedded market, as are Motorola's MPC500 series. They are aiming rather higher than the areas where ARM competes, which in turn is already aiming towards the higher end of the embedded space, but it's still the embedded market. Stuff like Motorola 6805s and PICs make up the bulk of the volume in the embedded market, but PowerPC takes up it's chunk of the dollars from this market.
Actually, Alpha is being actively killed by HP as it would have wiped the floor with their new poster-child, Itanium
Alpha has been in getting beaten to death in a long, slow and agonizing process over the past 7 years or so. This dates back to before Digital was bought out by Compaq and Intel (Intel bought a fab and a lot of Alpha technology in an odd legal settlement just before the Compaq deal... presumably the deal was made at Compaq's request). The merge with HP and the Itanium was just the final nail in the coffin for the long-suffering Alpha architecture.
In theory EPIC is all fine and dandy, but... why does it need 6MB of level 3 cache to show it?
Why? Because it's an in-order VLIW machine. The whole idea of VLIW is to simplify the processor core to make it simple, easy and consume very little power while making room for lots of cache and memory bandwidth. Same basic argument that was made for RISC over CISC years ago. Of course, some of this became a little screwed up because the Itanium isn't really simple or easy and it consumes a LOT of power.
There might not even be a 'better way' to design a general-purpose CPU.
Well, what we'ver really seen recently is that the ISA doesn't seem to matter that much. Just take a look at the 4 companies producing x86 chips these days. We have Intel, who's P4 design breaks down x86 instructions into micro-ops that are sent through a long pipeline. We have AMD who takes x86 instructions and repackages them as macro-ops and sends them through one of several somewhat shorter pipelines. We have VIA (using the old IDT/Centaur "Winchip" design) who are doing a pretty simple CISC chip in a fairly classic way (think: Pentium on steriods.. though not too many 'roids). And finally we have Transmeta doing a hybrid software/hybrid translation of x86 instructions into VLIW instructions. That's 4 different companies using 4 rather different methods of designing microprocessors, all using the same instruction set, 5 if you count the Intel Pentium-M (though that is kinda-sorta of halfway in between the P4 and the K7/K8 design).
In the end, AMD's Athlon processor probably has a lot more in common with the IBM PowerPC 970 than it does with Intel's P4 when you look at the internals. On the outside though, the P4 and the Athlon are basically the same (same ISA, very comperable performance and power consumption).
Anyway, as you mentioned, x86 is not really standing still. The combination of SSE(1/2/3) replacing the old stack-based FPU and x86-64/AMD64 adding 64-bit addressing and doubling the number of GPRs removes two of the last major architectural limitations of x86. There really just isn't that much left that's "wrong" with the architecture for people to complain about... not that that's ever stopped people from complaining!
If you look at SPEC CPU scores (about the only widely used cross-platform CPU tests), 10 years ago Alpha had x86 beat solid while SPARC, PA-RISC and MIPS were doing pretty well.
Now if you look at SPEC scores x86 has the two fastest CINT scores out there with Athlon64/Opteron and P4EE/Xeon. Those two chips are also two of the top 4 chips when it comes to CFP scores, with only the IBM Power4 and Intel Itanium2 being ahead. Alpha is no longer competitive, SPARC is getting it's butt whipped and MIPS has totally failed on the high-end and PA-RISC is on life support.
All those people predicting x86's demise are clearly out of touch with reality. x86 is not only continuing to do well, but it's doing BETTER now than it ever used to!
PowerPC is an instruction set that IBM uses for all of their current processors. POWER is two things: first it's an OLD ISA that they used to use long ago, and second it is a marketing name that IBM uses for their high-end PowerPC processors.
Despite popular belief, the "Power4" and "Power5" processors do NOT use the POWER ISA, they are PowerPC chips. Same as the PowerPC 970 chips used in Apple's new Macs and same as the PowerPC 405 used in the Nintendo Gamecube and Cisco routers.
Motorola also produces chips that use the PowerPC architecture, among many other ISAs.
I wonder if Microsoft has kept that old NT version which runs on PowerPC in anyways up to date?
Rumor has it that the first XBox2 development kits ran on Macs (PowerPC) running a custom port of WinNT.
I know this is mostly aimed at embedded devices
Don't forget that WinCE has supported PowerPC chips for ages. It's not like Microsoft is incapable of supporting PPC, there's just never been any demand for it on the desktop or server side.
If MS were to release it's server line for the Power5 or somesuch, how quickly would intel scramble to stay in Microsofts' good graces?
Considering that Microsoft would probably only get about 2 customers for such an operating system, I don't think Intel would be too worried. People who buy IBM Power5 systems are looking at the seriously high-end. They are looking for a complete package of hardware, software and support, so they are not going to go off and install Windows on the thing!
Intel has top-notch documentation, far and away the best in the industry. The only company that comes close is AMD. IBM's public documentation for their processors is absolutely abysmal in comparison. Maybe they ahve good documentation buried somewhere in the company, but they sure don't like sharing it with anyone.
As it stands now, PowerPC is no where near as "open" as x86 is, IBM has a LONG way to go.
My first thought is that this is nothing but a bunch of marketing BS, no substance at all.
Seriously, read the article, just what is IBM opening up? Answer: nothing that everyone else isn't already opening up.
The instruction set is still controlled by IBM, and while you are free to make your own PPC chips, it's not like that's anything new. Everyone is free to make their own SPARC chips as well, and from the looks of things SPARC has fewer restrictions than what IBM is proposing.
IBM will still license you the core, but that's hardly any different from what a half-dozen other chip markets will do using a wide variety of architectures.
So what does this buy you over x86? It's not like the x86 architecture is somehow *closed*. The ISA is fully documented and there are at least 4 companies producing x86 processors at the moment, possibly more if you look at the embedded space.
To me it sounds like nothing but a bunch of marketing BS trying to jump on some sort of open source bandwagon.
1) If you are doing anything in Lightwave by all means don't use AMD's XP:) There must be some major tweak they are missing.
It's called SSE2. Lightwave uses it, the AthlonXP doesn't support it. The chip also has the lowest memory bandwidth of any of these chips.
As for the scale thing, you're right. A lot of the processor performance they're seeing just doesn't matter much for todays applications. One could argue that they might help out for future applications that strain the processor a bit more, but it seems a bit pointless to spend a lot of money today on a CPU for software that might appear a year from now when a much faster CPU will be dirt-cheap.
4) With all of the tests there wasn't one compiler test:(
I'm sure that one of the multitude of other reviews out there did a compiler test or two. If all else fails, there is always SPEC CPU2000. One of the CINT sub-benches tests compiling performance with GCC. You have to do a bit of sorting by sub-test, but Ace's hardware have a nifty SPECmine tool that can help you in this regard.
So a single processor Opteron system with a PCI bus and AGP slot costing $1500 was a "workstation", but a dual-processor G5 with PCI-X costing $3000 was a "personal computer". Clearly these lines are more than a bit fuzzy.
As for power consumption, the Opteron and the PowerPC 970 are nearly identical clock for clock. The 2.0GHz PPC 970 has a maximum power consumption of about 70W, same as the Opteron (though neither are particularly well documented in this regard). The new PPC 970FX is a lower powered part, consuming only 37W maximum power at 2.0GHz, but even that isn't far off the lower power Opteron 246HE chips, running at 2.0GHz and consuming a maximum of 55W. AMD also plans on releasing a 30W Opteron running at 2.0GHz in the not-too-distant future.
In short, both are good chips, both target similar markets and both have similar power consumption numbers. The PPC970 has a slight edge in terms of size and cost at only 58M transistors vs. the Opteron's 105M transistors, but a lot of the Opteron's extra transistors are the extra cache (~60M transistors for 1MB of cache vs. ~30M transistors for the 512KB of the PPC970s cache) and the extra I/O stuff integrated onto the chip. In some applications the PPC970 may end up being a better choice, in others the Opteron would be a better choice.
Slashdot Mirror
Sun will somehow finish a significantly more complex processor when they give up on this one?
Uhh, Niagara is a MUCH simpler processor than the UltraSparc V! Where the US V was supposed to be a very complicated, high-end core, Niagara is just a whole bunch of fairly simple cores glued together.
I'm sure someone on /. has said that many times over, but it's not at all the case.
For those who are too lazy to read the article, Sun is NOT killing off the SPARC line, they are NOT discontinuing all their CPU production and they are NOT switching everything to AMD64 chips.
What Sun is doing is finally putting an end to their rather unsuccessful attempts to produce a single-threaded raw number crunching chip. Sun hasn't been successful at this for some time now (certainly since at least the UltraSparc II and probably for a while before then) and the UltraSparc V was just going to be another failure in this regard. No one buys Sun's for their raw number crunching performance anyway (since they stink in this regard), so this is really a pretty bright move by Sun. Really it's something they should have done a while ago.
The plan going forward is for Sun to work to their strengths. Their CPU division will produce highly multithreaded chips that are designed for server work, ie the sort of stuff that people buy Suns for in the first place. Their workstation line will be replaced by AMD64 systems since EVERYONE is moving their workstation line to x86 anyway. The only thing holding people to Sun workstations (and IBM or SGI workstations as well) was the lack of 64-bit capabilities on x86 chips, but that restriction is no more.
Sun will still need some SPARC workstation products for a while going forward to support customers with legacy Solaris software that can't easily be upgraded though. If they are smart, what Sun will do is buy some SPARC64-V chips from Fujitsu. This gives Sun faster chips for much lower cost then developping their own.
Did you ever wonder why no one sells x86 servers with more than 8 CPUs
You mean servers like this or IBM's plans detailed here? x86 servers with more than 8 processors definitely do exist, even if they are somewhat rare.
Well, one reason is the x86 architecture doesn't scale with a crap in a multiple-CPU box
That has very little to do with the processor itself and MUCH more to do with the supporting components. One problem that x86 chips have traditionally had is the lack of a high-bandwidth and low-latency bus for I/O, but with the Opteron that potential weakness is gone. Given decent supporting hardware AND software the Opteron can (and does) scale VERY well.
What they are doing is simply a change in strategy, and the right change IMO. Sun hasn't been competitive in raw number crunching and single-threaded performance for quite some time and the UltraSparc V wasn't going to be enough to save them. However they were spending a LOT of money to not be very successful. Sun had the second largest CPU development team in the world after Intel, yet companies like AMD and Fujitsu were producing faster (single-threaded) processors for much lower costs. In other words, it just wasn't working for Sun.
What IS working for Sun is multithreading performance. The UltraSparc IV now gives them up to 144 processor cores in a single image system, only SGI is doing more. They combine that really good I/O and solid software support and you have a pretty good solution for a high-end servers. It's not a very good choice for supercomputer-type applications (that's what SGI is after), nor is it very good for workstations, but Sun was getting killed in those markets anyway.
This announcement also ties back into the deal with AMD. While Sun hasn't been doing a very good job for workstation and number-crunching chips, AMD IS doing great here. The Opteron is a great chip for these sorts of tasks and fills in many of the wholes that could potentially be left by the death of the US V. Now all Sun needs is to get the software support up to par for x86-86 Solaris (as well as Linux and maybe even Windows) and they'll be in a reasonable position.
In short, in my mind this is the right decision by Sun. The only thing that I think is bad about it is that they waited so long. IMO they should have killed of the US V a couple years ago!
The Intel i875 does NOT include Gigabit ethernet in the north bridge (aka Memory Communications Hub, or MCH). What it has is a separate bus (CSA or Communication Streaming Architecture) that is designed to directly connect to a discrete gigabit ethernet controller. To the best of my knowledge, Intel is the only company producing those disctere CSA ethernet chips.
The only new thing about the RAID support is that this works with both SATA and Parallel ATAI drives together. Previous solutions could only use either SATA or parallel ATA in any given array. Not a huge advance, but a nice little extra.
Yeah, much better to have two or three chips in a machine where if any one of them die than the whole systme is useless! That's what we've got now, where most chipsets come with 2 or 3 discrete chips, and you better believe that if any one of them dies then your system won't boot.
nVidia didn't really have a choice in the matter, AMD yanked the memory controller on-die, making it basically impossible to design a board in the same way that they had designed the nForce and nForce2 IGPs.
Now, don't get me wrong, I think the integrated memory controller is a GREAT idea and definitely the way to go, but it does cause some problems for integrated video, particularly on the current Athlon64 chips with only a 64-bit 400MT/s memory bus.
Fortunately there is a potential solution, and it should result in even better integrated video when it's economically feasible. The solution is to hang the video memory right off the motherboard chipset. SiS is doing this now with their SiS760 chipset. In fact, they ahve a rather nifty design where you can either use the memory connected to the processor main memory controller (shitty performance but super-cheap), hang memory off the motherboard chipset (much better performance but more expenisve) or even a combination of the two (not much of an advantage, but it does allow you to put a small amount of fast memory on the motherboard but still have access to other memory when needed).
I suspect that nVidia will come up with a design like this in the future. If they really want to push things forward they might even make a chipset with eDRAM integrated right onto the die. This would give them TONS of bandwidth, though it would restrict them to a relatively small amount of memory on chip.
The Intel i875 chipsets integrated NIC is only a 10/100 chip. The Communication Streaming Architecture (CSA) bus is used to directly connect the chipset to an add-in NIC chip, by-passing any bandwidth and latency hit you might take if going through a shared bus.
The difference is perhaps a bit academic though, since Intel sells the NIC chip to you plug onto the far end of the CSA bus, and I wouldn't be at all surprised if they have some sort of deal where you can buy an i875 chipset together with an Intel 82547 CSA ethernet controller. As far as I know, Intel is the only company producing CSA ethernet controllers, so it's kind of like getting it as one "chipset".
So you think that somehow having all these features implemented by different companies and trying to bodge all their drivers together will INCREASE stability?
Compare a motherboard chipset from nVidia, a NIC chip from 3Com, a graphics chip from ATI, an IDE controller from Promise and a sound card from Creative Labs to getting ALL of those features from nVidia. Which situation do you think is more likely to be tested together and less likely to cause interoperability problems?
If I can get GOOD quality components integrated onto the motherboard and pay next to nothing for them I am VERY happy. On my old system I had tons of problems getting my Creative Labs sound card to work with my VIA motherboard chipset, and my no-name Tulip chipset NIC didn't want to play at all with my nVidia video card.
Now I've got an nVidia chipset board with integrated sound, NIC and video and it works VERY well. I've had MUCH better stability with this integrated solution than with discrete chips.
The fire at the resin plant was a total smoke-screen, it had a negligible effect on production or costs.
The DRAM shortage that occured at that time had a LOT of reasons associated with it, but the short version is that it all boiled down to supply and demand. Despite having a large chunk of the international DRAM market, none of the companies were making any money because prices were so low. So, to try and fix this, they decided to constrain the supply a bit. Supply goes down while demand was going up at the same time. End result? Huge increase in price. The resin plant fire was just a nice scapegoat to point blame at.
The Koreans broke the monopoly because they didn't worry about making any money. They figured that they would get marketshare first while their government propped the company up and then eventually start making money several years down the road. This worked fairly well for Samsung, who are now the worlds #1 memory manufacturer. It didn't work at all for LG Semiconductor or Hyundai Semi (now groupped together as Hynix). Both of those companies lost billions of dollars and they continue to lose billions of dollars, though the Korean government still props them up. Fairly recently they were found to violate some trade restrictions because of these government handouts and now need to pay fairly hefty levies to sell their products in the US.
In any case, while this is all slightly off-topic for the article, it is something that is going to be rather important to remember in the next 6 months or so. Several memory companies have announced plans to reduce production while at the same time advising that they will be unable to meet demand. In other words, they're doing it all over again, restricting supply in order to boost revenue (and maybe even make a profit, since most memory companies are not at all profitable). Expect memory prices to rise fairly significantly throughout the course of this year and don't be at all surprised if an earthquake in Taiwan or a resin plant fire in Japan is blamed for the hike.
No, the G5 doesn't have a 1GHz HT bus... or ANY Hypertransport bus for that matter.
It has a 1.0GT/s Elastic I/O bus, dual 32-bit wide unidrectional point to point connection used for both memory and other I/O.
This is quite inferior to the Opterons current 128-bit wide 400MT/s memory bus + 3 hypertransport buses for other I/O, each running at 1600MT/s and 16-bits in either direction.
The PowerPC 970 (aka G5 in Apple-speak) is a prefectly good chip, but when it comes to I/O it is very much outclassed by the Opteron. On the upside though, it has the Xeon beat cold, but that's not saying much. The crappy bus is a known shortcoming if the Xeon and the reason why those chips suck bilge water in 4 processor setups.
First point, Apple had exactly ZERO to do with developping Hypertransport. Nothing, nodda, zippo, zilch! Hypertransport is primarily an AMD developped technology with a little bit of help from the now defunct API (Alpha Processor Inc.). Apple may be part of the Hypertransport Consortium, but so are about 90 other companies that had nothing to dow ith the development of Hypertransport.
Second point, the PowerPC 970 does NOT use Hypertransport as it's bus! Hypertransport in the PowerMac G5 is ONLY used as an interconnect between the memory and processor controller and the other two I/O chips (at least one of which is actually an AMD chip).
The PPC 970 uses the Elastic I/O bus, designed and developped by none other than IBM. This is a dual 32-bit wide unidirectional point-to-point bus running at up to 1.0GT/s. The bus isn't all that well documented, so I'm not sure if it's a true 1.0GHz bus or a 500MHz DDR bus or a 250MHz QDR bus. I would guess it's 250MHz QDR, though the difference is somewhat accademic. Either way, the bus provides for up to 4.0GB/s of bandwidth in either direction and since it is point-to-point connection, the bus is not shared on dual-processor systems.
In the end, this bus is actually a lot like what AMD used to use on their AthlonXP and AthlonMP line. The only differences are that the PPC 970 bus runs at a higher effective data rate and it is a pair of 32-bit unidirectional buses rather than the single 64-bit bi-directional bus on the AthlonXP.
For the Intel side of things you get a 400MT/s (100MHz QDR) to 800MT/s (200MHz QDR) 64-bit wide bi-directional bus. Current Xeons top out at 533MT/s (133MHz QDR). Unlike the AthlonMP and PowerPC 970 bus, Intel uses a shared bus. This is why the Xeon doesn't scale too well going from one to two processors and scales pretty horribly when going from two to four processors (beyond 4 CPUs you need separate buses, crossbars and all sorts of other fancy things beyond the scope of this discussion). The next generation of Xeon, to be released anywhere between 1 and 9 months from now (depending on what source your look at) will go up to the same 800MT/s bus that the desktop P4s use, that should provide a fairly decent boost in performance for multiprocessor Xeon systems. That will give the Xeon up to 6.4GB/s of bandwidth (either upstream or downstream, but not at the same time).
Of course, when it comes to the absolute beast of moving data around for commodity hardware, you have to look to the Opteron. While the G5 may easily have the Xeon beat in this regard, the Opteron stomps over both of them quite handily.
First and foremost, the Opteron changes all the rules by moving the memory controller on-die. On the PPC 970 and Intel P4/Xeon the memory controller hangs off the memory and processor controller chip (often called a "Northbridge", a name that dates back to early PCI days). This means that they are sharing one bus for both their memory tranfic and general purpose I/O. On the Opteron the two buses are separate. It has a 128-bit wide, 400MT/s (6.4GB/s) memory bus AND not one but *THREE* 1600MT/s dual 16-bit unidirectional Hypertransport connections for all other I/O. That's 3.2GB/s in either direction for each of the three HT links. Plus, since it's a NUMA architecture, in multiprocessor systems this bandwidth adds together rather than being shared.
What's perahps even more important than the raw bandwidth advantage the Opteron has over other setups is the latency advantage. Since everything is integrated onto the processor it significantly reduces the latency for I/O. In many applications latency is actually more important than raw bandwidth.
Long story short, don't look at just the clock speeds (or even the effective clock speeds that the marketing people like to toss around), there's a lot more too it than that. All three of these chips (PowerPC 970, Opteron and Xeon) have various advantages and disadvantages, but when it comes to I/O, the Opteron is far and away the leader of
Given Elbrus' history of delivering products, my guess is that this won't actually ship for a good 3-5 years.
I'd MUCH rather use Intel's XScale chip, that also runs at 500MHz, consumes only 500mW and also runs Linux and Windows (WinCE and Windows Mobile at least). Ohh, and it's shipping now, not 3-5 years from now.
There are plenty of other neat chips in similar power consumption ranges as well. IBM makes some PowerPC chips to compete, PMC Sierra has some MIPS chips and about 50 companies make fast but low powered ARM chips. There have even been a few other companies making low-power SPARC chips before, though they most have died out due to lack of market. I somehow doubt that Elbrus will fare any better.
Someone could probably double processor speed every 12 month instead of 18
Ironically enough, "Moore's Law" really DID specify a time span of 12 months! Of course that 12 month doubling thing didn't hold for very long, so the "law" was modified to 18 months and more recently to "about 18 to 24 months". Not really much of a law.
It's perhaps also important to point out that Moore never said anything about computing efficieny, but rather the number of transistors that you could put on one chip at any given price point. For example, Intel's new Prescott P4 processor isn't really any faster than the Northwood P4 processor that proceeded it, yet it has more than twice as many transistors. Moore's observation is holding true with this chip, transistor count did go up exponentially, however processor performance has not going up along with it.
Ok, I know complaining about unoptimized software is the popular thing to do on /., but honestly, why both optimizing software for fast processing?
Think of it, these days at least 99% of the biggest bottleneck in a computer system by a LONG margin is situated on the far side of the keyboard. You can optimize Word all to hell, make it process all my commands blazingly fast and yet it probably still won't manage to shave even 1 second off the amount of time it takes me to write a technical report.
Really what we need is software with GOOD functionality, not heavily optimized software. Programs with very efficient and usuable UIs will beat out software heavily optimized for fast executation but with a poor UI any day.
PowerPC chips are most definitely used in the embedded market! What the heck do you think powers Cisco routers? Or for that matter, the hardware diagnostics on Sun's Opteron-based V20z server? Hell, those two rovers doing their thing on Mars are using embedded PowerPC processors.
IBM's 4xx line of PowerPC chips are very much targetted at the embedded market, as are Motorola's MPC500 series. They are aiming rather higher than the areas where ARM competes, which in turn is already aiming towards the higher end of the embedded space, but it's still the embedded market. Stuff like Motorola 6805s and PICs make up the bulk of the volume in the embedded market, but PowerPC takes up it's chunk of the dollars from this market.
Actually, Alpha is being actively killed by HP as it would have wiped the floor with their new poster-child, Itanium
Alpha has been in getting beaten to death in a long, slow and agonizing process over the past 7 years or so. This dates back to before Digital was bought out by Compaq and Intel (Intel bought a fab and a lot of Alpha technology in an odd legal settlement just before the Compaq deal... presumably the deal was made at Compaq's request). The merge with HP and the Itanium was just the final nail in the coffin for the long-suffering Alpha architecture.
In theory EPIC is all fine and dandy, but ... why does it need 6MB of level 3 cache to show it?
Why? Because it's an in-order VLIW machine. The whole idea of VLIW is to simplify the processor core to make it simple, easy and consume very little power while making room for lots of cache and memory bandwidth. Same basic argument that was made for RISC over CISC years ago. Of course, some of this became a little screwed up because the Itanium isn't really simple or easy and it consumes a LOT of power.
There might not even be a 'better way' to design a general-purpose CPU.
Well, what we'ver really seen recently is that the ISA doesn't seem to matter that much. Just take a look at the 4 companies producing x86 chips these days. We have Intel, who's P4 design breaks down x86 instructions into micro-ops that are sent through a long pipeline. We have AMD who takes x86 instructions and repackages them as macro-ops and sends them through one of several somewhat shorter pipelines. We have VIA (using the old IDT/Centaur "Winchip" design) who are doing a pretty simple CISC chip in a fairly classic way (think: Pentium on steriods.. though not too many 'roids). And finally we have Transmeta doing a hybrid software/hybrid translation of x86 instructions into VLIW instructions. That's 4 different companies using 4 rather different methods of designing microprocessors, all using the same instruction set, 5 if you count the Intel Pentium-M (though that is kinda-sorta of halfway in between the P4 and the K7/K8 design).
In the end, AMD's Athlon processor probably has a lot more in common with the IBM PowerPC 970 than it does with Intel's P4 when you look at the internals. On the outside though, the P4 and the Athlon are basically the same (same ISA, very comperable performance and power consumption).
Anyway, as you mentioned, x86 is not really standing still. The combination of SSE(1/2/3) replacing the old stack-based FPU and x86-64/AMD64 adding 64-bit addressing and doubling the number of GPRs removes two of the last major architectural limitations of x86. There really just isn't that much left that's "wrong" with the architecture for people to complain about... not that that's ever stopped people from complaining!
If you look at SPEC CPU scores (about the only widely used cross-platform CPU tests), 10 years ago Alpha had x86 beat solid while SPARC, PA-RISC and MIPS were doing pretty well.
Now if you look at SPEC scores x86 has the two fastest CINT scores out there with Athlon64/Opteron and P4EE/Xeon. Those two chips are also two of the top 4 chips when it comes to CFP scores, with only the IBM Power4 and Intel Itanium2 being ahead. Alpha is no longer competitive, SPARC is getting it's butt whipped and MIPS has totally failed on the high-end and PA-RISC is on life support.
All those people predicting x86's demise are clearly out of touch with reality. x86 is not only continuing to do well, but it's doing BETTER now than it ever used to!
PowerPC is an instruction set that IBM uses for all of their current processors. POWER is two things: first it's an OLD ISA that they used to use long ago, and second it is a marketing name that IBM uses for their high-end PowerPC processors.
Despite popular belief, the "Power4" and "Power5" processors do NOT use the POWER ISA, they are PowerPC chips. Same as the PowerPC 970 chips used in Apple's new Macs and same as the PowerPC 405 used in the Nintendo Gamecube and Cisco routers.
Motorola also produces chips that use the PowerPC architecture, among many other ISAs.
I wonder if Microsoft has kept that old NT version which runs on PowerPC in anyways up to date?
Rumor has it that the first XBox2 development kits ran on Macs (PowerPC) running a custom port of WinNT.
I know this is mostly aimed at embedded devices
Don't forget that WinCE has supported PowerPC chips for ages. It's not like Microsoft is incapable of supporting PPC, there's just never been any demand for it on the desktop or server side.
If MS were to release it's server line for the Power5 or somesuch, how quickly would intel scramble to stay in Microsofts' good graces?
Considering that Microsoft would probably only get about 2 customers for such an operating system, I don't think Intel would be too worried. People who buy IBM Power5 systems are looking at the seriously high-end. They are looking for a complete package of hardware, software and support, so they are not going to go off and install Windows on the thing!
Uhh.. you mean like these Pentium 4 and Itanium 2 docs?
Intel has top-notch documentation, far and away the best in the industry. The only company that comes close is AMD. IBM's public documentation for their processors is absolutely abysmal in comparison. Maybe they ahve good documentation buried somewhere in the company, but they sure don't like sharing it with anyone.
As it stands now, PowerPC is no where near as "open" as x86 is, IBM has a LONG way to go.
My first thought is that this is nothing but a bunch of marketing BS, no substance at all.
Seriously, read the article, just what is IBM opening up? Answer: nothing that everyone else isn't already opening up.
The instruction set is still controlled by IBM, and while you are free to make your own PPC chips, it's not like that's anything new. Everyone is free to make their own SPARC chips as well, and from the looks of things SPARC has fewer restrictions than what IBM is proposing.
IBM will still license you the core, but that's hardly any different from what a half-dozen other chip markets will do using a wide variety of architectures.
So what does this buy you over x86? It's not like the x86 architecture is somehow *closed*. The ISA is fully documented and there are at least 4 companies producing x86 processors at the moment, possibly more if you look at the embedded space.
To me it sounds like nothing but a bunch of marketing BS trying to jump on some sort of open source bandwagon.
Again, RTFA! They stated several times where multithreaded benchmarks were being used.
1) If you are doing anything in Lightwave by all means don't use AMD's XP :) There must be some major tweak they are missing.
It's called SSE2. Lightwave uses it, the AthlonXP doesn't support it. The chip also has the lowest memory bandwidth of any of these chips.
As for the scale thing, you're right. A lot of the processor performance they're seeing just doesn't matter much for todays applications. One could argue that they might help out for future applications that strain the processor a bit more, but it seems a bit pointless to spend a lot of money today on a CPU for software that might appear a year from now when a much faster CPU will be dirt-cheap.
4) With all of the tests there wasn't one compiler test :(
I'm sure that one of the multitude of other reviews out there did a compiler test or two. If all else fails, there is always SPEC CPU2000. One of the CINT sub-benches tests compiling performance with GCC. You have to do a bit of sorting by sub-test, but Ace's hardware have a nifty SPECmine tool that can help you in this regard.
So a single processor Opteron system with a PCI bus and AGP slot costing $1500 was a "workstation", but a dual-processor G5 with PCI-X costing $3000 was a "personal computer". Clearly these lines are more than a bit fuzzy.
As for power consumption, the Opteron and the PowerPC 970 are nearly identical clock for clock. The 2.0GHz PPC 970 has a maximum power consumption of about 70W, same as the Opteron (though neither are particularly well documented in this regard). The new PPC 970FX is a lower powered part, consuming only 37W maximum power at 2.0GHz, but even that isn't far off the lower power Opteron 246HE chips, running at 2.0GHz and consuming a maximum of 55W. AMD also plans on releasing a 30W Opteron running at 2.0GHz in the not-too-distant future.
In short, both are good chips, both target similar markets and both have similar power consumption numbers. The PPC970 has a slight edge in terms of size and cost at only 58M transistors vs. the Opteron's 105M transistors, but a lot of the Opteron's extra transistors are the extra cache (~60M transistors for 1MB of cache vs. ~30M transistors for the 512KB of the PPC970s cache) and the extra I/O stuff integrated onto the chip. In some applications the PPC970 may end up being a better choice, in others the Opteron would be a better choice.