Your description isn't terribly accurate either. Back in the days of planar semiconductors, the process node (eg. 45nm, 32nm, 22nm) referred to the minimum feature size, which was also at least approximately the minimum gate length. There are other features, particularly some metal line widths in the Back End Of Line (BEOL) that were also close to the nominal node size. The problem in modern technology is that as you scale down the gate length, short-channel effects, particularly Drain Induced Barrier Lowering (DIBL) begins to dominate. This effect degrades transistor performance, such that it is no longer practical to scale gate lengths much below ~20nm. We could easily print 7nm gates, but the resulting devices would be power hungry, hot and slow, not exactly the combination anybody wants!
Now having said that, some gate scaling is still possible, but whereas in the past, gates were routinely scaled by ~30% between each node, today gate scaling is on the order of a few percent and even that requires a lot of work to optimize the device junctions, so as to constrain DIBL. Nevertheless, there are still gains to be had by scaling other aspects of the device. Moving to Finfets, where the gate wraps around a "fin" of silicon provides two advantages. First, the fin itself has a vertical dimension, which corresponds roughly to the width of conventional planar device. This means that if we want more current per unit area, instead of widening the transistor, we can make the fin taller (within limits). So, we are kind of scrunching the transistors into a smaller space. The other and perhaps more important advantage is that because the gate wraps around a very thin fin of silicon, it has better control of the silicon channel, reducing DIBL and other short channel effects. Thus, thinning down the fin provides not only a density benefit, but also a performance benefit.
In today's technology nodes, the smallest dimensions no longer correspond to the gate length, but they do correspond roughly to the fin size. As far as I'm aware, all of today's 7nm processes consist of Fins in the 6-9nm range. I believe there are also some metal lines that are of similar size, which helps in providing more flexibility in routing the connections between various circuits.
Finally, regarding comparing technologies between fabs, the comparison is somewhat complicated by some specific design choices about the basic SRAM and Logic cells and how they are allowed to be connected. In particular, Intel's 10nm process, uses a very aggressive BEOL. This allows them to make small cells of comparable density to the 7nm process of Samsung and TSMC. By contrast, Samsung and TSMC have a relaxed BEOL, so they sacrifice some density, but retain a lead in the raw transistor performance. The end result is that intel's 10nm process and 7nm processes of their competitors are all very comparable.
Also - R&D is one of the last things sent abroad. You outsource things that are easy and repetitive - which R&D is not.
I've actually seen quite a bit of R&D work outsourced to Russia (to former nuclear scientists) and more recently India. However, usually, this is theoretical or modeling and simulation work that doesn't require significant investments in sensitive equipment or the infrastructure to support it. On the other hand, most of the work IBM is talking about appears to be in advanced materials science. which tends to be pretty equipment intensive and is thus unlikely to be moved from their current locations in the U.S. and Europe.
What makes you think any of that 3 billion would be spent in the US regardless?
Well, the IBM press release specifically states the money will go to Yorktown and Albany, New York, Almaden, California, and Europe. (Most likely this means IBM-Zurich, where the Scanning-Tunelling Microscope or STM was invented).
Potassium is a metal. It should be quite conductive. I doubt you'd want to use it as a dielectric (insulator). Furthermore, it's generally considered a harmful contaminant in Fabrication of semiconductor devices.
Potassium (K) as a dopant? I don't think so. I'm pretty sure Sodium and Potassium are metallic fast-diffusers that you want to keep as far away from the devices as possible. In silicon they act as electron or hole recombination centers, destroying carrier lifetimes, and significantly degrading performance. For conventional CMOS processing the typical dopants are Boron (p-type) and Phosphorus, Arsenic, or maybe Antimony (n-type). Note how these are either the Group III or Group V elements on the periodic table and thus have either an extra or missing electron in the valence shell compared to Silicon, which is what gives them the favorable doping properties.
Well, if they just released 22nm, Moore's law would predict a 14nm release in about 2 years, but from a fab equipment standpoint, they would already need to be working on it now, so most of the equipment is likely already in place today.
As for the difficulty of going from 22nm to 14nm, the scaling is not so much the problem. Rather, it's that everyone (except intel, who did it at 22nm) is transitioning from planar to finfet technology. You are absolutely correct that that transition is very challenging and could cause delays. But that's more about process readiness than equipment readiness. On the other hand, IBM has been working in collaboration with GLOBALFOUNDRIES and Samsung, both of whom are reportedly pretty far along on 14nm, so 14nm may be closer than some think.
Don't forget Power7+ (2012), which came out at 32nm. Intel released their latest and greatest i7v2 series at 22nm in February. The highest end chips at a list price of ~$6K, just barely beat the performance of Power7+. IBM's Power8 chips were just released this month at 22nm. They roughly double the performance of Power7+, and have a 30-50% performance advantage over i7v2 in raw per core performance. They also have significantly more L3 and L4 cache per core, a better memory architecture, and significantly better multi-thread support (SMT). IBM says this can give a more than 80x benefit over x86 for some applications, and even more for memory intensive tasks.
The bottom line, yes IBM is behind intel in litho node introduction, but is significantly ahead on the high-end server chip front. (It's much easier to release a low-end part at 14nm than a high end part.) Their East Fishkill fab is definitely not 10-years obsolete, in fact it should be capable of releasing 14nm chips in the near future and would not require major upgrades for the 10nm node.
Hmm... Did somebody forget to tell IBM? They released their 32nm based z-series chips a couple years back, and appear to be on track to release their next 22nm based chip within the next year.
Power 8 gives:
30% higher single-thread FPU performance compared to x86 at the same clock speed (based on SPECfp_rate2006)
50% higher single-thread integer performance compared to x86 at the same clock speed (based on SPECint_rate2006)
Plus the Power 8 clock speed will scale up to 25% higher for even more performance. Add in significantly more L3 cache, 8 threads/core (compared to 2/core for x86) and up to 12 cores/chip. IBM has a monster on their hands. It will never find it's way into a laptop, but for servers and HPC applications, it's game on.
Digital signals do not transmit further than Analog signals! In fact, the range of a watchable signal is severely reduced. The clarity of the digital signal is significantly better and remains nearly perfect until the edge of the transmission range, but beyond that it completely degrades, whereas the analog signal is of poor quality, but still viable for many more miles.
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Your description isn't terribly accurate either. Back in the days of planar semiconductors, the process node (eg. 45nm, 32nm, 22nm) referred to the minimum feature size, which was also at least approximately the minimum gate length. There are other features, particularly some metal line widths in the Back End Of Line (BEOL) that were also close to the nominal node size. The problem in modern technology is that as you scale down the gate length, short-channel effects, particularly Drain Induced Barrier Lowering (DIBL) begins to dominate. This effect degrades transistor performance, such that it is no longer practical to scale gate lengths much below ~20nm. We could easily print 7nm gates, but the resulting devices would be power hungry, hot and slow, not exactly the combination anybody wants!
Now having said that, some gate scaling is still possible, but whereas in the past, gates were routinely scaled by ~30% between each node, today gate scaling is on the order of a few percent and even that requires a lot of work to optimize the device junctions, so as to constrain DIBL. Nevertheless, there are still gains to be had by scaling other aspects of the device. Moving to Finfets, where the gate wraps around a "fin" of silicon provides two advantages. First, the fin itself has a vertical dimension, which corresponds roughly to the width of conventional planar device. This means that if we want more current per unit area, instead of widening the transistor, we can make the fin taller (within limits). So, we are kind of scrunching the transistors into a smaller space. The other and perhaps more important advantage is that because the gate wraps around a very thin fin of silicon, it has better control of the silicon channel, reducing DIBL and other short channel effects. Thus, thinning down the fin provides not only a density benefit, but also a performance benefit.
In today's technology nodes, the smallest dimensions no longer correspond to the gate length, but they do correspond roughly to the fin size. As far as I'm aware, all of today's 7nm processes consist of Fins in the 6-9nm range. I believe there are also some metal lines that are of similar size, which helps in providing more flexibility in routing the connections between various circuits.
Finally, regarding comparing technologies between fabs, the comparison is somewhat complicated by some specific design choices about the basic SRAM and Logic cells and how they are allowed to be connected. In particular, Intel's 10nm process, uses a very aggressive BEOL. This allows them to make small cells of comparable density to the 7nm process of Samsung and TSMC. By contrast, Samsung and TSMC have a relaxed BEOL, so they sacrifice some density, but retain a lead in the raw transistor performance. The end result is that intel's 10nm process and 7nm processes of their competitors are all very comparable.
Also - R&D is one of the last things sent abroad. You outsource things that are easy and repetitive - which R&D is not.
I've actually seen quite a bit of R&D work outsourced to Russia (to former nuclear scientists) and more recently India. However, usually, this is theoretical or modeling and simulation work that doesn't require significant investments in sensitive equipment or the infrastructure to support it. On the other hand, most of the work IBM is talking about appears to be in advanced materials science. which tends to be pretty equipment intensive and is thus unlikely to be moved from their current locations in the U.S. and Europe.
What makes you think any of that 3 billion would be spent in the US regardless?
Well, the IBM press release specifically states the money will go to Yorktown and Albany, New York, Almaden, California, and Europe. (Most likely this means IBM-Zurich, where the Scanning-Tunelling Microscope or STM was invented).
Potassium is a metal. It should be quite conductive. I doubt you'd want to use it as a dielectric (insulator). Furthermore, it's generally considered a harmful contaminant in Fabrication of semiconductor devices.
Potassium (K) as a dopant? I don't think so. I'm pretty sure Sodium and Potassium are metallic fast-diffusers that you want to keep as far away from the devices as possible. In silicon they act as electron or hole recombination centers, destroying carrier lifetimes, and significantly degrading performance. For conventional CMOS processing the typical dopants are Boron (p-type) and Phosphorus, Arsenic, or maybe Antimony (n-type). Note how these are either the Group III or Group V elements on the periodic table and thus have either an extra or missing electron in the valence shell compared to Silicon, which is what gives them the favorable doping properties.
Well, if they just released 22nm, Moore's law would predict a 14nm release in about 2 years, but from a fab equipment standpoint, they would already need to be working on it now, so most of the equipment is likely already in place today.
As for the difficulty of going from 22nm to 14nm, the scaling is not so much the problem. Rather, it's that everyone (except intel, who did it at 22nm) is transitioning from planar to finfet technology. You are absolutely correct that that transition is very challenging and could cause delays. But that's more about process readiness than equipment readiness. On the other hand, IBM has been working in collaboration with GLOBALFOUNDRIES and Samsung, both of whom are reportedly pretty far along on 14nm, so 14nm may be closer than some think.
Don't forget Power7+ (2012), which came out at 32nm. Intel released their latest and greatest i7v2 series at 22nm in February. The highest end chips at a list price of ~$6K, just barely beat the performance of Power7+. IBM's Power8 chips were just released this month at 22nm. They roughly double the performance of Power7+, and have a 30-50% performance advantage over i7v2 in raw per core performance. They also have significantly more L3 and L4 cache per core, a better memory architecture, and significantly better multi-thread support (SMT). IBM says this can give a more than 80x benefit over x86 for some applications, and even more for memory intensive tasks. The bottom line, yes IBM is behind intel in litho node introduction, but is significantly ahead on the high-end server chip front. (It's much easier to release a low-end part at 14nm than a high end part.) Their East Fishkill fab is definitely not 10-years obsolete, in fact it should be capable of releasing 14nm chips in the near future and would not require major upgrades for the 10nm node.
Hmm... Did somebody forget to tell IBM? They released their 32nm based z-series chips a couple years back, and appear to be on track to release their next 22nm based chip within the next year.
Sounds like what you really want are NVIDIA CUDA on CAPI: http://www.prnewswire.com/news...
... Only on Power8 from IBM.
Power 8 gives:
30% higher single-thread FPU performance compared to x86 at the same clock speed (based on SPECfp_rate2006)
50% higher single-thread integer performance compared to x86 at the same clock speed (based on SPECint_rate2006)
Plus the Power 8 clock speed will scale up to 25% higher for even more performance. Add in significantly more L3 cache, 8 threads/core (compared to 2/core for x86) and up to 12 cores/chip. IBM has a monster on their hands. It will never find it's way into a laptop, but for servers and HPC applications, it's game on.
Digital signals do not transmit further than Analog signals! In fact, the range of a watchable signal is severely reduced. The clarity of the digital signal is significantly better and remains nearly perfect until the edge of the transmission range, but beyond that it completely degrades, whereas the analog signal is of poor quality, but still viable for many more miles.