This would be a good example, except (a) a lot of people complain about the cost of bottled water and (b) gas, around here, is about $1.50.... water is about $0.39, bottled. So, yeah, use the same kind of evocative metaphor, with less lies, and it'll make a good point.
The Rad750, btw, is a deeply cool chip. Once it's mature enough to start using for scientific-level stuff, it will be a real revolution in what we can do. One of the limitations with Hubble was that it had so little processing, a full data dump needed to be done for even checking orientation; there was no ability to offload processing to the sat. If the 750, or something similar (not that I know of anything too similar) is up there for our next big telescope, it will make a real difference in the efficiency of how it is used.
However, many processors (the G3/750FX comes to mind) allow you to address cache as physical memory, allowing exactly what the grandparent mentioned. You'll still need an external memory controller, though, to get stuff from ROM for boot purposes.
Um, you're right about the two ways to get good performance... but loop unrolling for an 8MB cache is a totally different animal than unrolling for a 1MB cache (you start talking about doing multiple-level unrolling, and hoisting invariants through n, as opposed to 1, loop boundary). Similarly, an efficient instruction stream is different when you have 2 ALU's, 2 L/S units, and 160 rename registers than when you have 2 combined, and 16. Scaling of these features on a processor leads to a lot more than linear, or even quantitative, scaling in compiler strategies.
Umwhat? In what way is ctrl-alt-delete a hardware interrupt? It's branched out of the standard key handler earlier than other keys, and generates a (different) software interrupt, if that's what you meant... but it sure ain't what you said.
Control-Apple-Power works with the power button on the main computer, although it may require more-than-average contortionary skills (or, alternately, more-than-average desk design skills).
On OS X, I keep 5 icons (my working set) in the task bar. I keep my active documents (2-3 icons max) on the desktop, where I can get with expose. I use voice recognition to start any of about 10 apps, or run basic scripts, and I use audio feedback wherever possible to save screen space (someone logging on, then, reads me there name, rather than beeping and forcing me to change windows). For everything else, I use launchbar, which may be the best shareware program ever written.
Um, if the root servers shouldn't handle a request for.elvis, who the heck should? I mean, that's there purpose... to inform a requestor if a given tld exists, and if so, where. You can't cache non-existence, since things change.
Very, very true. Personally, I'm a stack machine fan... but everyone should really know about microcontrollers, stack machines, transputers, bitslice processors, and them what-are-they-calleds that switch threads every cycle to eliminate the cost of latency without cache.
It's extremely unlikely that prescott will need any additional stages in decode. It's feasible, but not likely, that it will need a delay stage between decode and issue, but there's already one around there. So these extra stages are probably all visible even to instructions already in the icache.
Were you appropriately tuning GCC's (nearly infinite) number of optimization flags?
If you did make an effort to optimize with GCC, I'd be very interested in seeing the program, and knowing what compiler you ended up with... I'm in the mood to add some more optimizations to gcc ppc, and I finally have a G4 to profile with, instead of having to chud everything.
If your p4, p3, or athlon hang, at all, something is wrong. Hardware should never, in this day and age, cause hangs, unless you're using your computer in a harsh environment (inside your microwave, perhaps?).
Many PICs and other processors with memory entirely onboard (or even just static memory offboard that has a maximum speed higher than the processor) will show a linear relationship between performance and clock speed.
For high end processors, of course, you are correct.
Slashdot Mirror
Your logic makes baby jesus cry.
Does DVI-D even support WUXGA? I vaguely recall the DVI spec ending at 1600x1200, which is (in theory) one reason apple is going with ADC.
This would be a good example, except (a) a lot of people complain about the cost of bottled water and (b) gas, around here, is about $1.50.... water is about $0.39, bottled. So, yeah, use the same kind of evocative metaphor, with less lies, and it'll make a good point.
The Rad750, btw, is a deeply cool chip. Once it's mature enough to start using for scientific-level stuff, it will be a real revolution in what we can do. One of the limitations with Hubble was that it had so little processing, a full data dump needed to be done for even checking orientation; there was no ability to offload processing to the sat. If the 750, or something similar (not that I know of anything too similar) is up there for our next big telescope, it will make a real difference in the efficiency of how it is used.
However, many processors (the G3/750FX comes to mind) allow you to address cache as physical memory, allowing exactly what the grandparent mentioned. You'll still need an external memory controller, though, to get stuff from ROM for boot purposes.
Um, you're right about the two ways to get good performance... but loop unrolling for an 8MB cache is a totally different animal than unrolling for a 1MB cache (you start talking about doing multiple-level unrolling, and hoisting invariants through n, as opposed to 1, loop boundary). Similarly, an efficient instruction stream is different when you have 2 ALU's, 2 L/S units, and 160 rename registers than when you have 2 combined, and 16. Scaling of these features on a processor leads to a lot more than linear, or even quantitative, scaling in compiler strategies.
Score: 3, Insightful?
I'd be more accepting of Score: 2, Contrived.
It is not a hardware signal. It is a software interrupt, an exception.
Umwhat? In what way is ctrl-alt-delete a hardware interrupt? It's branched out of the standard key handler earlier than other keys, and generates a (different) software interrupt, if that's what you meant... but it sure ain't what you said.
Control-Apple-Power works with the power button on the main computer, although it may require more-than-average contortionary skills (or, alternately, more-than-average desk design skills).
Um, if software 'disables' a feature I use, I don't stop using the feature... I ues software that has the features I care about, instead.
Hmm, maybe I'll upgrade my iPod to a Nomad. Or maybe I'll just mod my iPod, make it more like a Nomad... how much were bricks selling for at Walmart?
On OS X, I keep 5 icons (my working set) in the task bar. I keep my active documents (2-3 icons max) on the desktop, where I can get with expose. I use voice recognition to start any of about 10 apps, or run basic scripts, and I use audio feedback wherever possible to save screen space (someone logging on, then, reads me there name, rather than beeping and forcing me to change windows). For everything else, I use launchbar, which may be the best shareware program ever written.
Presumably, the best person for the job isn't one who makes careless mistakes.
Libraries-of-Congress/sec
Abbreviated locs. Now we know what the real problem with the beagle was; it didn't have enough lox!
Um, if the root servers shouldn't handle a request for .elvis, who the heck should? I mean, that's there purpose... to inform a requestor if a given tld exists, and if so, where. You can't cache non-existence, since things change.
That's okay, you couldn't come up with a good heatsink haiku either.
Colorforth: Where am I? What was I drinking last night?
As I mentioned, I use chud... and it's great for profiling, but being able to run the code for real is nice, too.
Very, very true. Personally, I'm a stack machine fan... but everyone should really know about microcontrollers, stack machines, transputers, bitslice processors, and them what-are-they-calleds that switch threads every cycle to eliminate the cost of latency without cache.
I are.
It's extremely unlikely that prescott will need any additional stages in decode. It's feasible, but not likely, that it will need a delay stage between decode and issue, but there's already one around there. So these extra stages are probably all visible even to instructions already in the icache.
Were you appropriately tuning GCC's (nearly infinite) number of optimization flags?
If you did make an effort to optimize with GCC, I'd be very interested in seeing the program, and knowing what compiler you ended up with... I'm in the mood to add some more optimizations to gcc ppc, and I finally have a G4 to profile with, instead of having to chud everything.
If your p4, p3, or athlon hang, at all, something is wrong. Hardware should never, in this day and age, cause hangs, unless you're using your computer in a harsh environment (inside your microwave, perhaps?).
Many PICs and other processors with memory entirely onboard (or even just static memory offboard that has a maximum speed higher than the processor) will show a linear relationship between performance and clock speed.
For high end processors, of course, you are correct.