together with arachne-pnr and yosys, you could put in place a fully open source pipeline to program those little rascals, from Verilog to bitstream.
this cold be also the starting path toward a similar open source hardware design, suppose. if that's road is not encumbered by patents about this kind of "gate layout", of course.
Slashdot Mirror
having an open "gate array" or FPGA with fully diclosed bistream would be really relevant. morover it could have a RISC-V hard core side by side.
actually there's anyway a reverse engineering effort of the bitstream for the iCE40 Lattice smaller FPGA (up to 8K LUT), it's project icStorm
http://www.clifford.at/icestor...
together with arachne-pnr and yosys, you could put in place a fully open source pipeline to program those little rascals, from Verilog to bitstream.
this cold be also the starting path toward a similar open source hardware design, suppose. if that's road is not encumbered by patents about this kind of "gate layout", of course.