Everyone missuses the term "Moore's Law," and thinks that it means computers get twice as fast ~18 months. It doesn't mean that. It never did.
Moore's law says that the DENSITY of transistors on silicon doubles every 18 months -- that means you can cram twice as many transistors on the chip in the same amount of space as you could 18 months ago. Moore never said anything about frequency, nor "x-times as fast" nor any of the other bastardized versions that people have come up with.
One problem with asynchronous logic
on
Clockless Computing
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· Score: 2, Interesting
For any large project (such as an MPU), using asynchronous logic isntead of synchronous for the entire thing means it goes from being "merely" really-really-hard to damn-near-impossible.
I bet the compiler guys are gonna have fun statically scheduling 64 instructions each cycle! (if you can't tell, I'm dripping with sarcasm, as Intel is even having a tough time scheduling 6 per cycle...though this is a DSP, so that makes it's application much better).
It can hurt performance because the larger the cache, the higher it's latency is going to be. Of course, the larger it is, the higher the hit-rate in that cache, so it's less likely to have to go down another level in the memory hierarchy.
Using more caches of varying sizes is actually better than a monolithic cache, for reasons you described. If there are more caches, the primary one can focus upon low-latency, the second for high-bandwidth, and the third for high-hit-rate.
But yes, it is indeed 35Mb of caches, though it's worthy of note that the L2 cache is off-die.
It wouldn't be stealing an idea. This idea has been around for a long time in academia. Maybe the poster forgot this, but the POWER4 from IBM does this, and comes with 32Mb of L3 cache, plus an ondie shared L2 cache. The idea isn't new, it's known as CMP (Chip-level Multi-Processing). Really, "SMP on a chip" is merely called CMP.
Also, though Sun has decided not to use the MAJC architecture for anything (they were hoping to try to get it to become a video-accelerator, but that's not even going to happen, most likely), that too was fully spec'ed out to have multiple cores on a chip...it's really nothign new:)
The longstanding rumour is that AMD will be coming out with a dual-hammer processor (ie, CMP). In academia, the idea has been used frequently as well.
The idea of using CMP isn't even that big a deal to most consumers. While it would be nice for AMD to come out with a chip that does multithreading (merely because it increases real-world throughput quite a bit, depending upon the type of multithreading), the average PC running windows 9x/ME/ XP Consumer won't be able to multithread anyway. The only reason for AMD to multithread is for the server-space, which is what they're aiming for with the hammer series...but I digress.
Um...yeah. nVidia hasn't always been a leader in the field. They have publically said that their first video card was a complete and utter failuer, because they chose to accelerate quadrilaterals instead of triangles, and triangles became the standard.
Why bother with a GF3 though? Yes, it has some more features that alleviate bandwidth some, but it would have made a larger die, and therefore cost more, and only given marginally better performance (though admittedly, the quality would probably have been better). But, given that the integrated video is already bandwidth limited why should they stuff a bigger, more expensive core in there that wouldn't perform much better?
I don't write in DX8. I'm not saying it's not good. I'm not saying it is good. I don't have any experience with programming for it. What I'm trying to prove is that while P implies Q, Q does not necessarily imply P. Simple logic.
The point of the post I responded to tried to claim that volume implied great quality, which it does not. If it did, then betamax would VHS is superior.
Of course, in cases of x86, and VHS, they won out to strong user bases, and marketing (and in the case of x86, very strong engineering to get around some of the issues). I'm not saying DX is crap. I was saying that the post that got a high moderating did nothing to prove the claim.
The only thing I think sucks about WINE is that it's a novel solution to the must-have-MS-programs problem. Of course, wouldn't it be nice NOT to need WINE? I mean, wouldn't it be nice if we could do everything and uses _standards_ without WINE?
WINE allows people to keep writing software for Win32, and ignore the Linux. Is that what you want?
You say that sheer volume proves it's easy. ASM on x86 isn't exactly the nicest thing. Or, do you _like_ being limited to 8 general purpose registers, and a crappy FPU stack?
If we go by sheer volume, x86 must be a freaking dream to write software for, and it must be some heavenly architecture!
They pointed out that they got their processor and motherboard from Intel. They even mentioned things like that several times, and apologized for not having another system. Some people can't afford new athlons....like me:-\ (damned socket 7 piece of...)
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Everyone missuses the term "Moore's Law," and thinks that it means computers get twice as fast ~18 months. It doesn't mean that. It never did.
Moore's law says that the DENSITY of transistors on silicon doubles every 18 months -- that means you can cram twice as many transistors on the chip in the same amount of space as you could 18 months ago. Moore never said anything about frequency, nor "x-times as fast" nor any of the other bastardized versions that people have come up with.
For any large project (such as an MPU), using asynchronous logic isntead of synchronous for the entire thing means it goes from being "merely" really-really-hard to damn-near-impossible.
I bet the compiler guys are gonna have fun statically scheduling 64 instructions each cycle! (if you can't tell, I'm dripping with sarcasm, as Intel is even having a tough time scheduling 6 per cycle...though this is a DSP, so that makes it's application much better).
It can hurt performance because the larger the cache, the higher it's latency is going to be. Of course, the larger it is, the higher the hit-rate in that cache, so it's less likely to have to go down another level in the memory hierarchy.
Using more caches of varying sizes is actually better than a monolithic cache, for reasons you described. If there are more caches, the primary one can focus upon low-latency, the second for high-bandwidth, and the third for high-hit-rate.
But yes, it is indeed 35Mb of caches, though it's worthy of note that the L2 cache is off-die.
It wouldn't be stealing an idea. This idea has been around for a long time in academia. Maybe the poster forgot this, but the POWER4 from IBM does this, and comes with 32Mb of L3 cache, plus an ondie shared L2 cache. The idea isn't new, it's known as CMP (Chip-level Multi-Processing). Really, "SMP on a chip" is merely called CMP.
:)
Also, though Sun has decided not to use the MAJC architecture for anything (they were hoping to try to get it to become a video-accelerator, but that's not even going to happen, most likely), that too was fully spec'ed out to have multiple cores on a chip...it's really nothign new
The longstanding rumour is that AMD will be coming out with a dual-hammer processor (ie, CMP). In academia, the idea has been used frequently as well.
The idea of using CMP isn't even that big a deal to most consumers. While it would be nice for AMD to come out with a chip that does multithreading (merely because it increases real-world throughput quite a bit, depending upon the type of multithreading), the average PC running windows 9x/ME/ XP Consumer won't be able to multithread anyway. The only reason for AMD to multithread is for the server-space, which is what they're aiming for with the hammer series...but I digress.
Um...yeah. nVidia hasn't always been a leader in the field. They have publically said that their first video card was a complete and utter failuer, because they chose to accelerate quadrilaterals instead of triangles, and triangles became the standard.
Why bother with a GF3 though? Yes, it has some more features that alleviate bandwidth some, but it would have made a larger die, and therefore cost more, and only given marginally better performance (though admittedly, the quality would probably have been better). But, given that the integrated video is already bandwidth limited why should they stuff a bigger, more expensive core in there that wouldn't perform much better?
You realize that the quote you're refering to is 4.5 years old, right?
I don't write in DX8. I'm not saying it's not good. I'm not saying it is good. I don't have any experience with programming for it. What I'm trying to prove is that while P implies Q, Q does not necessarily imply P. Simple logic.
The point of the post I responded to tried to claim that volume implied great quality, which it does not. If it did, then betamax would VHS is superior.
Of course, in cases of x86, and VHS, they won out to strong user bases, and marketing (and in the case of x86, very strong engineering to get around some of the issues). I'm not saying DX is crap. I was saying that the post that got a high moderating did nothing to prove the claim.
The only thing I think sucks about WINE is that it's a novel solution to the must-have-MS-programs problem. Of course, wouldn't it be nice NOT to need WINE? I mean, wouldn't it be nice if we could do everything and uses _standards_ without WINE?
WINE allows people to keep writing software for Win32, and ignore the Linux. Is that what you want?
You say that sheer volume proves it's easy. ASM on x86 isn't exactly the nicest thing. Or, do you _like_ being limited to 8 general purpose registers, and a crappy FPU stack?
If we go by sheer volume, x86 must be a freaking dream to write software for, and it must be some heavenly architecture!
if you read the article, they got the case for like, 169 bucks or so. They didn't actually buy a G4 system.
They pointed out that they got their processor and motherboard from Intel. They even mentioned things like that several times, and apologized for not having another system. Some people can't afford new athlons....like me :-\ (damned socket 7 piece of...)