Sorry, but your post shows that you have no understanding of what mainframes are used for.
Supercomputers are used for high performance technical computing. Mainframes, on the other hand are used when you need high reliability/availability. When someone talks about 5-nines reliability, they are saying a system is up 99.999% of the time - equivalent to a couple minutes per year. The systems that achieve this do what is called fault-tolerant computing. It is done by having integrated redundant hardware along with the appropriate specialized software to deal with it.
You won't find any supercomputer or PC that does this. This is why there will *always* be a market for mainframes. It may not be a huge market, but it's still a market.
Anyone ever read "Cryptonomicon" by Neil Stephenson? One of the main characters has exactly this problem. He's cranks out a lot of really creative stuff when he gets laid. Put another way, his genious was inversely proportional to the amount of time since his last sexual encounter... (Self encounters didn't really count)
>Yay, $30 to replace a $2 IC and $0.50 connector. Not that the connector counts, as you did have to pay for a USB connector anyways.
I'm not sure what it costs by itself, but it sure isn't $30. I just bought a logitech keyboard and mouse and both came with PS/2 to USB adaptors. The keyboard cost $30! Meanwhile, you can do the same thing for parallel port.
Either way, I would much rather have extra USB or Firewire ports than a PS/2 or parallel port. For the 0.01% of users who need this functionality, I'm sure someone will supply a legacy port PCI card or adaptors. And of course, you can buy your stuff from another company.:^) The board real estate isn't the issue, it's the back of the machine real estate. Parallel ports are rather large.
At a minimum laptops should forgo the legacy ports. They're just not necessary.
While I'm not a Microsoft fan, it is really foolish to think that Linux is iherently that much better than an MS product. Honestly, I wouldn't want either doing brain surgery on me! First of all, I'd want fault-tolerant hardware. Then, the software should be designed using formal methods and stringent verification.
Would anything less be acceptible. We're talking about a bug being a life or death issue. While working for Compaq, some folks from the Tandem unit gave a talk. They run their computer hardware in lockstep *and* the operating system is designed for ultra-high reliability. Even so, they will not certify the systems for medical use because the stakes are so high.
I'm not against the concept of a robot doing surgery. However, very high standards must be observed in the design of such a system
Let's say for a minute that these so-called patent claims are valid. Even if that were the case, just because a site uses Linux does not mean that they would owe anything to the owners of those patents. Linux users are merely using a product which somebody else "stole". In other words, SCO would have to go after the people who wrote the code in question.
Remember when a company called Franklin copied the Apple IIe? Apple sued and put them out of business. That didn't mean that all of the computers they had sold could not be used! Same goes for Linux users.
Only patent infringers could be made to pay fees/royalties, not the users themselves.
On the other hand, is it possible to infringe on a patent when the product you make is free? Does one have to profit from patent infringement for a lawsuit to be valid?
Either way, I say this whole story is a big load of crap.
I bought an RCA Scenium DRS7000N. It's a combination DVD player and PVR. They call it a digital media player because it handles DVD, JPEG, and MP3.
One of the best features is the GuidePlus Gold programming guide that gives you the equivalent of the TiVo program guide for *FREE*. Programming info is either downloaded over cable or over the air. I paid $500 for it. Since it it one of the first of its kind, I'm sure prices will come down.
There are other options which include DVD burning, but RCA is the only one to have the GuidePlus program guide. I highly recommend it at 4/5 stars.(There are a few relatively minor issues with the machine)
Re:Alpha EV7 will kick its butt... More this Frida
on
New SGI Altix 3000
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· Score: 1
Oops, I misspoke. ASCI Q is 30 Teraflops, not 5.
Alpha EV7 will kick its butt... More this Friday
on
New SGI Altix 3000
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· Score: 1
HP is due to announce availability of the Alpha Marvel platform based on the 21364 (EV7). As a server platform it will have excellent performance.
Initially, it will be available with up to 16 processors, with later support for up to 128 in a single box. Larger single-image systems can be constructed with Quadrics switches. For operating system, it will run Tru64, Linux, or OpenVMS.
EV7 was built for bandwidth - how's this: 8 Rambus channels for 12.8GB/s peak mem bandwidth(6GB/s read or write bandwidth), and 3.2GB/s PCI I/O bandwidth. In addition to this, each chip has 4 interprocessor ports to support glueless multi-processing. Each link supports 6.4GB/s total or 3.2GB/s in a single direction. The chips are connected through these ports in a 2D torus configuration.
With current RIMMs, each EV7 can support up to 4GB of memory, though later this should increase to 16GB. This system is Rambus done right.
This system forms the basis for the 5 Teraflop ASCI Q supercomputer. Let's see an Itanium system match that. Check out HP's press release in a few days.
Therein lies the problem. If anything, the Geek is more dedicated to the bottom line than the Suit, because a more elegant solution is a part of or even the foundation of a sound business model, especially in the long run.
That's nice in theory but companies like DEC proved that excellent engineering doesn't necessarily translate into profit. There was a company started by a geek and run by geek culture. They could have done with a little more business culture.
IBM has been using partially-depleted SOI which actually increases leakage current and therefore increases standby power.
Fully-depleted SOI should have lower leakage current due to better control over the transistor channel. While Intel doesn't call it SOI, they announced their "terahertz transistor" sometime last year which is actually a fully-depleted SOI device.
Another way to reduce leakage power would be to use dual-gates when building the transistor. There is a decent amount of research going on in this field. Dual gate would offer large decreases in leakage current.
Andy Grove wasn't saying that Moore's law is dead today or even next year. I'm sure Intel is doing just fine at the moment. While there are design tricks you can do to reduce power, leakage will become a bigger issue for everybody. It can't be avoided, as you can't avoid the laws of physics.
Don't worry. We still have several more years of Moore's Law ahead of us.
It seems to me that most posters seem to have latched onto the headline "The End of Moore's Law" and missed the point of what Andy Grove said.
Traditionally, power consumption on chips has been primarily governed by power supply voltage and clock speed. Power due to standby current (aka "leakage") was not a huge portion of total power consumption. Traditional power-saving techniques on chips usually involves using conditional/gated clocking so that unused parts of the chip can be disabled. These power-saving techniques are useless against leakage current. As chips move to 0.07 micron and below, leakage current will account for more than 50% of total power consumption. This means that you could stop the on-chip clocks and still be consuming lots of power.
This problem will not be restricted to high-performance CPUs, but will also need to be addressed by ASIC designs.
One point on this, though. The point of my original post was that in the time since the Intel deal, very few people have left. (as in well below normal levels) I think it is partly due to the sexy new project and partly due to the economy.
Re:Most Alpha engineers are still with Intel
on
End In Sight For Alpha
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· Score: 2, Informative
Since I work in the group, I know firsthand. Since I still work for the group, I won't give specific numbers.
Every company out there has some level of attrition each year. In the cpu design business, it tends to happen at the end of a project. The industry average when not in a recession is about 10% annually. Every major Alpha implementation (EV4, EV5, EV6, and EV7) has had several engineers leave after more or less completing the project. Previous to the Compaq merger with DEC, the Alpha attrition rate was well below industry average. Afterwards during the hot dot-com economy, we approached the 10% industry average. (silicon valley is actually worse on average) One thing to keep in mind that while several very experienced engineers have left, it is still a very experienced design team.
Absolute numbers don't actually mean anything by themselves. You could lose the best 10 engineers or the worst 10 engineers. Where will you ever truly get "evidence" about something like this? Surely not from the average internet columnist. I wanted to set the story straight, since it seems to be a popular myth to propagate in tech columns. None of these columnists has had sufficient inside knowledge on which to base their claims. I couldn't prove it either unless you came to work here. %^)
Most Alpha engineers are still with Intel
on
End In Sight For Alpha
·
· Score: 2, Informative
>> Intel bought the technology, so if their new 64-bit processor (which shatters compatibility anyhow) doesn't perform well enough, they could just start making Alphas and call them their own.
"I doubt. Intel bought the patents and the documents,
but most engineers left. Intel has lousy employee relationship, so they wouldn't be able to reproduce the in-house expertise Digital, Silicon Graphics, HP (before merge) had and that IBM, Sun now have."
That is a widely spread fiction. Only a small handful out of several hundred engineers have left since the Compaq deal with Intel. In fact, there are 3 or four who are Intel Fellows. That is essentially a VP-level engineering position, the highest possible. True engineers can't resist working on something new and sexy and Intel gave it to them. They get to design the next generation Itanium from the ground up. As a result, most of the engineers elected to stay.
We'll have to see how it all turns out in a few years.
Actually, no. Intel gets to hire the former Alpha Design team and gets access to a subset of the intellectual property. However, HP still owns all of the rights to the Alpha Architecture and all of its implementations.
Alphas were priced out of what market? Maybe they are too expensive for PC's, but they are definitely competetive with the other RISC architectures. They are aimed at the high end, not the low-end.
Marketing is the main problem.
Re:How could Alpha benefit IA64?
on
Intel's Big Chip
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· Score: 1
There are plenty of good engineers who have moved to Intel. There are several still at Compaq. Yes, some good engineers have left, but most stayed. (which kind of surprised me)
Just because Intel put a stupid marketing name on a feature doesn't make it a useless feature. That just means that Intel knows how to sell a product. IBM did not do SMT that I know of. They did the more basic form of multithreading.
Re:How could Alpha benefit IA64?
on
Intel's Big Chip
·
· Score: 1
The Itanium line probably won't benefit from "Alpha features" per se, however it can benefit greatly from the Alpha design team experience. That is the big thing that Intel got out of the deal with Compaq is the design team.
There is no doubt that the first Itanium was a disaster at Intel. However, that doesn't mean that follow-on chips can't do better. While IA64 is nowhere near as clean as Alpha, I believe it is still better than x86. With the experience from the first two Itanium chips, (Merced and McKinley) the former Alpha design team should be able to do the architecture justice. The Alpha group has great expertise in doing high-performance full-custom design. Combine that with an intelligent, balanced microarchitecture and you have a good chip. Good system design is more important than the instruction set.(though the instruction set can help, of course!)
By the way, SMT stands for Simultaneous Multi-Threading. That means that instructions for multiple execution threads can be issued and executing at the same time. Conventional multi-threading chips as proposed by IBM(and others) involve dynamically switching between threads, but only executing code from one at a time. The only thing this saves is a context switch. In real-world terms, this means that old-MT gives you about a 30% performance boost, while SMT gives you a 2-2.5x performance boost. That would be for transaction processing applications. Other applications get a significant boost, though not as much on average. It's not just a marketing gimmick! It was a central feature of the next Alpha. Check out the Microprocessor papers being presented at ISSCC this week and you'll see a paper about the last Alpha chip.
Slashdot Mirror
Supercomputers are used for high performance technical computing. Mainframes, on the other hand are used when you need high reliability/availability. When someone talks about 5-nines reliability, they are saying a system is up 99.999% of the time - equivalent to a couple minutes per year. The systems that achieve this do what is called fault-tolerant computing. It is done by having integrated redundant hardware along with the appropriate specialized software to deal with it.
You won't find any supercomputer or PC that does this. This is why there will *always* be a market for mainframes. It may not be a huge market, but it's still a market.
Anyone ever read "Cryptonomicon" by Neil Stephenson? One of the main characters has exactly this problem. He's cranks out a lot of really creative stuff when he gets laid. Put another way, his genious was inversely proportional to the amount of time since his last sexual encounter... (Self encounters didn't really count)
Apparently, the evil one is branching out...
I'm not sure what it costs by itself, but it sure isn't $30. I just bought a logitech keyboard and mouse and both came with PS/2 to USB adaptors. The keyboard cost $30! Meanwhile, you can do the same thing for parallel port.
Either way, I would much rather have extra USB or Firewire ports than a PS/2 or parallel port. For the 0.01% of users who need this functionality, I'm sure someone will supply a legacy port PCI card or adaptors. And of course, you can buy your stuff from another company. :^) The board real estate isn't the issue, it's the back of the machine real estate. Parallel ports are rather large.
At a minimum laptops should forgo the legacy ports. They're just not necessary.
While I'm not a Microsoft fan, it is really foolish to think that Linux is iherently that much better than an MS product. Honestly, I wouldn't want either doing brain surgery on me! First of all, I'd want fault-tolerant hardware. Then, the software should be designed using formal methods and stringent verification.
Would anything less be acceptible. We're talking about a bug being a life or death issue. While working for Compaq, some folks from the Tandem unit gave a talk. They run their computer hardware in lockstep *and* the operating system is designed for ultra-high reliability. Even so, they will not certify the systems for medical use because the stakes are so high.
I'm not against the concept of a robot doing surgery. However, very high standards must be observed in the design of such a system
Remember when a company called Franklin copied the Apple IIe? Apple sued and put them out of business. That didn't mean that all of the computers they had sold could not be used! Same goes for Linux users.
Only patent infringers could be made to pay fees/royalties, not the users themselves.
On the other hand, is it possible to infringe on a patent when the product you make is free? Does one have to profit from patent infringement for a lawsuit to be valid?
Either way, I say this whole story is a big load of crap.
One of the best features is the GuidePlus Gold programming guide that gives you the equivalent of the TiVo program guide for *FREE*. Programming info is either downloaded over cable or over the air. I paid $500 for it. Since it it one of the first of its kind, I'm sure prices will come down.
There are other options which include DVD burning, but RCA is the only one to have the GuidePlus program guide. I highly recommend it at 4/5 stars.(There are a few relatively minor issues with the machine)
Oops, I misspoke. ASCI Q is 30 Teraflops, not 5.
Initially, it will be available with up to 16 processors, with later support for up to 128 in a single box. Larger single-image systems can be constructed with Quadrics switches. For operating system, it will run Tru64, Linux, or OpenVMS.
EV7 was built for bandwidth - how's this: 8 Rambus channels for 12.8GB/s peak mem bandwidth(6GB/s read or write bandwidth), and 3.2GB/s PCI I/O bandwidth. In addition to this, each chip has 4 interprocessor ports to support glueless multi-processing. Each link supports 6.4GB/s total or 3.2GB/s in a single direction. The chips are connected through these ports in a 2D torus configuration.
With current RIMMs, each EV7 can support up to 4GB of memory, though later this should increase to 16GB. This system is Rambus done right.
This system forms the basis for the 5 Teraflop ASCI Q supercomputer. Let's see an Itanium system match that. Check out HP's press release in a few days.
Therein lies the problem. If anything, the Geek is more dedicated to the bottom line than the Suit, because a more elegant solution is a part of or even the foundation of a sound business model, especially in the long run.
That's nice in theory but companies like DEC proved that excellent engineering doesn't necessarily translate into profit. There was a company started by a geek and run by geek culture. They could have done with a little more business culture.
IBM has been using partially-depleted SOI which actually increases leakage current and therefore increases standby power.
Fully-depleted SOI should have lower leakage current due to better control over the transistor channel. While Intel doesn't call it SOI, they announced their "terahertz transistor" sometime last year which is actually a fully-depleted SOI device.
Another way to reduce leakage power would be to use dual-gates when building the transistor. There is a decent amount of research going on in this field. Dual gate would offer large decreases in leakage current.
Whoa, tone down the boldface.
Andy Grove wasn't saying that Moore's law is dead today or even next year. I'm sure Intel is doing just fine at the moment. While there are design tricks you can do to reduce power, leakage will become a bigger issue for everybody. It can't be avoided, as you can't avoid the laws of physics.
Don't worry. We still have several more years of Moore's Law ahead of us.
It seems to me that most posters seem to have latched onto the headline "The End of Moore's Law" and missed the point of what Andy Grove said.
Traditionally, power consumption on chips has been primarily governed by power supply voltage and clock speed. Power due to standby current (aka "leakage") was not a huge portion of total power consumption. Traditional power-saving techniques on chips usually involves using conditional/gated clocking so that unused parts of the chip can be disabled. These power-saving techniques are useless against leakage current. As chips move to 0.07 micron and below, leakage current will account for more than 50% of total power consumption. This means that you could stop the on-chip clocks and still be consuming lots of power.
This problem will not be restricted to high-performance CPUs, but will also need to be addressed by ASIC designs.
One point on this, though. The point of my original post was that in the time since the Intel deal, very few people have left. (as in well below normal levels) I think it is partly due to the sexy new project and partly due to the economy.
Since I work in the group, I know firsthand. Since I still work for the group, I won't give specific numbers.
Every company out there has some level of attrition each year. In the cpu design business, it tends to happen at the end of a project. The industry average when not in a recession is about 10% annually. Every major Alpha implementation (EV4, EV5, EV6, and EV7) has had several engineers leave after more or less completing the project. Previous to the Compaq merger with DEC, the Alpha attrition rate was well below industry average. Afterwards during the hot dot-com economy, we approached the 10% industry average. (silicon valley is actually worse on average) One thing to keep in mind that while several very experienced engineers have left, it is still a very experienced design team.
Absolute numbers don't actually mean anything by themselves. You could lose the best 10 engineers or the worst 10 engineers. Where will you ever truly get "evidence" about something like this? Surely not from the average internet columnist. I wanted to set the story straight, since it seems to be a popular myth to propagate in tech columns. None of these columnists has had sufficient inside knowledge on which to base their claims. I couldn't prove it either unless you came to work here. %^)
We'll have to see how it all turns out in a few years.
Actually, no. Intel gets to hire the former Alpha Design team and gets access to a subset of the intellectual property. However, HP still owns all of the rights to the Alpha Architecture and all of its implementations.
Alphas were priced out of what market? Maybe they are too expensive for PC's, but they are definitely competetive with the other RISC architectures. They are aimed at the high end, not the low-end. Marketing is the main problem.
There are plenty of good engineers who have moved to Intel. There are several still at Compaq. Yes, some good engineers have left, but most stayed. (which kind of surprised me)
Just because Intel put a stupid marketing name on a feature doesn't make it a useless feature. That just means that Intel knows how to sell a product. IBM did not do SMT that I know of. They did the more basic form of multithreading.
The Itanium line probably won't benefit from "Alpha features" per se, however it can benefit greatly from the Alpha design team experience. That is the big thing that Intel got out of the deal with Compaq is the design team. There is no doubt that the first Itanium was a disaster at Intel. However, that doesn't mean that follow-on chips can't do better. While IA64 is nowhere near as clean as Alpha, I believe it is still better than x86. With the experience from the first two Itanium chips, (Merced and McKinley) the former Alpha design team should be able to do the architecture justice. The Alpha group has great expertise in doing high-performance full-custom design. Combine that with an intelligent, balanced microarchitecture and you have a good chip. Good system design is more important than the instruction set.(though the instruction set can help, of course!) By the way, SMT stands for Simultaneous Multi-Threading. That means that instructions for multiple execution threads can be issued and executing at the same time. Conventional multi-threading chips as proposed by IBM(and others) involve dynamically switching between threads, but only executing code from one at a time. The only thing this saves is a context switch. In real-world terms, this means that old-MT gives you about a 30% performance boost, while SMT gives you a 2-2.5x performance boost. That would be for transaction processing applications. Other applications get a significant boost, though not as much on average. It's not just a marketing gimmick! It was a central feature of the next Alpha. Check out the Microprocessor papers being presented at ISSCC this week and you'll see a paper about the last Alpha chip.