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Intel's Big Chip
DeadBugs writes "News.com has an article about the size of the upcoming revision for the Itanium. The "McKinley" chip will be 464 square millimeters which would make it one of the largest ever produced. Most of this is due to the 64 bit registers and 3MB of Level 3 Cache. There is also a link to an article about "Chivano" an Itanium which will include concepts from the Alpha architecture"
Intel gets it right! Morce_Cache==Good_Thing. Was anyone else scratching their head over the 8k of level 1 cache on the Pentium 4?
Joe
It's not the size of the chip that matters, but how many numbers it can crunch. It isn't like users see the chip in the course of normal computer use. It's all hidden away behind the case.
i wonder if the oversized chip will lead to particular cooling difficulties(i.e. standard fans and heatsinks can't cool the entire surface area)...
lysergically yours
so 21.5 mm to a side? Thats barely over 4 square centimeters... physically smaller than the pentium 75 I just threw away? Or does this not count the housing or whatever where the pins and heatsink and everything else are mounted? I don't follow.
Or did you mean 464 mm square?
Best Slashdot Co
The size is required to have enough heat dissipation area.
Is this the start of the manly "Mine is bigger than yours" battle?
Too expensive and nothing really new, i would rather overclock my 32bit P4 processsor than getting a big same, but Madison sounds really cool, i can wait until 2004.
Sigs are for morons... Wait a minute...
Straight and to the point. Nice.
psmylie's dictionary: Godzillion (noun) Any number large enough to destroy Tokyo
> Another analyst said, "Jesus, that's big."
I love the reporting style, this is GREAT!
This line also appeared in the article about my [censored].
lysergically yours
Our new CPU is so big it will CRUSH the competition... No, really. We mean it quite literally :)
if Pentiums cost $50 to produce, will these cost 6x as much as a Pentium?
hmmm... sorry Intel, I'll stick to AMD till I hit the lotto, or have some other good reason to spend money like it was going out of style.
THERE IS NO DATA. THERE IS O
Sounds silly to me. By the time you get out to the 3rd level of cache, on a 1GHz core, there should be enough slow down that chip to chip interconnect will be adequately fast.
Either Intel has actually put research into this and discovered that it's a good tradeoff performancewise, or they've still got marketing driven engineering and someone said "wow! over 3 MB of on chip cache!"
Any guess on the wattage? Has Intel broken 100 Watts on their upward march of hot chips?
Start Running Better Polls
The Athlon chips i have are around 2-2.5 inches on a side, however, the die in the middle is quite small, i'd estimate it it be 200-250 square mm, so a 400+ square millimeter is huge, compared to that.
Anyone have any exact numbers for the chips? I didn't get a ruler out to measure it.
Try looking at a CPU some time. There's one big square, and one small rectangular thing. That small thing is the actual CPU die. That connects to the big PCB or ceramic thing (the big square) which spreads the interconnects out to the big pins.
I measured my chip is 2.15 cm...
when folded in half.
The bigger and faster the better. All this means less time before I can replace all my K6's with used P III's 1Ghz for very little money.
all my K6's
the Buffalo Pan-American Exposition or by "deranged anarchists"
tcd004
Sounds neato to me, but since Dual XP's and such are also starting to get very acceptable pricing around now...
Sure, 64 bit is nice... but a good multiprocessor solution might do wonders too.
Then again, I may be missing the point.. but if a company can get a Dual XP or Dual P4 for less, they would probably go for that... Oracle and such is probably already optimized for such configurations... and since XP's and P4's have a good reputation (eg reliable), it might give them more confidence.
Somehow, I just don't think this would be such a big profit hit for them.
Ace's Hardware has this bit with more information including links to an Intel presentation.
"Slide 22 of the presentation features a die photo of McKinley. The large 3 MB L3 cache is notable, and according to the presentation, it consumes 20% less area than traditional designs and is overall 85% efficient (~70% for traditional designs)."
And here's a story with the photo from that same article (no need to download 2.5 meg pdf...)
-Russ
Me
Just for some minor clarifications: The 464 mm squared is the area of the actual cpu die. Like the little square on top of an athlon. So 2 cm per side die is kind of huge for a processor. The actual processor out of the box would have to be much larger than previous models. Next, 3 MB cache sounds nice, but L3? It may be on die, but by that point the clock reduction probably makes it perform equivalently to a 256 k L1 cache, or a 512 or larger L2. Not that it won't help a lot for complicated instructions, and it's probably less expensive/difficult to engineer to hook a larger amount of cache to a slower pipeline than to add more cache deeper into the cpu's core. 64-bit cpu's will be important in the future, but only when compatible apps and OS designs become mainstream.
Way back when the 386 was hot stuff there was a series of mother boards that had a 64K of cache that was outperformed by a board that had 16K of cache.
How? The 16K board cache was four way set associative. This allowed for the CPU to determine in one clock cycle if the next instruction was in cache. The 64K cache design could not always do this. Thus it was often slower. Why not make the 64K cache 4 way set associative? Cost. The overhead in silcon and motherboard space made this impossible at the time.
Straight from the articled in reference to the size of the new chip:
;-)
"Another analyst said, 'Jesus, that's big.'"
What a great quote...simple and to the point. What would we ever do with out descriptive investigative journalism and technical expertise of this nature!!!
Beer is proof that God loves us and wants us to be happy. -- Benjamin Franklin
Wouldn't it take longer for signals to get from place to place on a bigger chip?
Such is the infinite Grace of Popeye.
For the article
Madison is expected to come out in 2003 and run between 1.2GHz and 1.6GHz, according to sources.
I wonder how Intel expects people to adopt Itanium-based processors considering
that x86 processors will be running at 4GHz in 2003.
I really think these companies could do better. Intel bought the rights to Alpha last year, but they won't be using any of it until 2004. We know from benchmarks that a 667mhz Alpha was capable of trashing a Itanium 800mhz, and there's a lot more powerful Alpha's than that. Intel is too much into marketing from my view.
"And we have seen and do testify that the Father sent the Son to be the Savior of the World"
1 John 4:14
Yeah, right. Intel is the big player. Right.
;)
My calculator's processor has 64 bit registers. You think i'm trolling? Check it out for yourself:
google search
There are a lot more (and more powerful) procs out there, but this one just seems more appropriate for intel bashing
Looking for people to chat about multicopters, coding, music. skype: gtsiros
..perhaps we're trying to get back to the good ol' days when you could walk around inside your computer....
or maybe they're taking the term "big iron" a little too seriously..
At that size, a smallish mug should fit nicely on it. No use wasting all that heat!
Don't current Athlon XP's include some parts or work-alikes of the Alpha processors?? I thought there was some discussion of this in relation to the AGP/memory page size issues...
5 years ago I read an article about Merced, on of the points of the article was that the EPIC instruction set would allow Intel to scale the number of execution units in the CPU. High end Merceds would have more execution units and be faster. The addition logic was said to be a better use of transistors (die space) than large caches.
Now Intel brings McKinley with massive L3 cache. I know that in large SMP machines memory access is a big bottleneck, and apparently Intel is confident that they can Fab this beast, but still, does massive L3 cache indicate a cludge - that Intel can't get the expected performance from EPIC and need a quick cache fix?
Or is it merely a matter that Intel can Fab 'em and in servers the L3 really is that useful that you'd use 1/3 or your die space for it?
"464 square millimeters which would make it one of the largest ever produced....due to the 64 bit registers." 464^.5=21.54mm a side.
64bits/21.54mm=2.97 bits/mm
They've GOT to start using smaller wavelengths!
Don't you get it? page widening posts are making people NOT want to read at -1....not only is it as dumb as a fucking turd, but it also has adverse affects on trolls....fucking idiot
Did anyone bother getting the Diamond Mako?
It's a Psion Revo sold by Diamond with no real difference to the Revo other than the name.
I picked mine up for $100 from TigerDirect, and promptly lost it in under 2 months. But it was great while it lasted.
In Soviet Russia, the television watches YOU!
I'll do a re-read on it tonight. I haven't touched it since 1998.
It seems that if they are putting that much cache on the die it must not be for grins and giggles.
Space is at such a premium, they would not have undertaken adding that much cache without a great deal of thought.
http://www.lostcircuits.com/cpu/hp_pa8800
8 70 0wp.pdf
Has 3Mbyte L1 cache and 32Mbyte L2 cache and
a transistor count of 300 million.
To quote:
"The HP PA-8800 L1 cache is probably the biggest L1 that ever existed so far with separate 750 KBytes of data and instruction cache for each core. This results in no less of 4 blocks of ¾ MB density each for a total of an unprecedented 3 MB L1 cache, physically twice as much as the combined L1+L2 on IBM's Power4. Accordingly, the transistor count of the HP-PA8800 is with 300 Million transistors almost twice as high as the 170 Million transistors of the IBM Power4 and results in a die size of 23.6x15.5 mm2 or 361 mm2. The L2 cache of the PA-8800 is off-chip and consists of four 72 Mbit "1 Transistor SRAM" chips developed by Enhanced Memory Systems.
http://www.cpus.hp.com/technical_references/PA-
has a roadmap of the hp-pa and Itanium chips so
really there is nothing new or exciting to report
that hasn't already been said 9 months ago.
... if you can't run the apps.
Intel x86 is restricted to 48-bit addressing (with segment registers), and practically 64GB with modern OSes. (http://linux-mm.org/)
If I want more than 64GB of addressable physical memory (which I do for some apps), then who cares if you can give me a 32-bit x86 running at 900GHz, it's not going to do diddly squat for me, since _going over the PCI bus_ for swap is going to kill me vs a 1.6GHz 64-bit processor. And since you need to go over the PCI bus just to get to a pseudo-disk stuffed with RAM, that solution is still bogus.
I see your point that this isn't what Joe Blow's gonna put on his desk. But the improved address space is definately a big win, and that's assuming that they can't ramp up the clock speed in a hurry.
Now that you mention AMD. It has been roumoured last week all over the net that intel has a backup plan, an P4 with 64bit extenstions
.18.
.18 and the next generation is on .13. note that this can make a differce of a factor 2 (13^2/18^2= 0.52)
os.opinion article
news.com
by the way, the amd hammer is expected to 105 mmm^2 on 130 nanometer (.13).
the current amd MP (palomino) has a die size of 129mm on
the original P4 has a die size of 217mm and is now at 150 mm^2.(with a bigger cache)
Note that the original article does mention the 424 size is on
Last I heard, Intel may have dug themselves a hole with Itanium. It's incompatibility with existing apps means that there is no desktop demand to drive economy of scale. Therefore the price isn't coming down and the price/performance is not improving faster than the older, "inferior" technology. How will they escape this death spiral?
sPh
I read PC Magazine just because I've been subscribing to it for a decade or so. Anyway, recently they had an article (I forget which issue) in which they talked about the Itanium. There, they showed a demo of Maya 4 running on the Itanium.
All I can say is wow. This means power. I'm looking forward to some of outcomes of stuff done on this (super)chip.
PayPal $$ if you sign up for free offers (eBay, cred cards, e
More cache = larger die size = low yeild per wafer = very expensive processors = fewer sales.
This giant die is going to be very hard to produce in any quantity. CPU makers must balance acceptable cache levels with acceptable production costs.
Like titanics. lol "the Itanics" have sunk.
#!/bin/sh
/tmp/icc.hack.
/tmp/icc.hack.
/tmp/icc.hack.
/tmp/icc.hack. icc
/tmp/icc.hack.
##
## haX0red Intel C/C++ Compiler
##
## This simple shell script will h4x0r the icc compiler so that
## it skips the check for a valid license file. I was inspired
## to do this because of the asshole Intel engineer at
## LinuxWorld 2002 who did everything he could to dodge
## my questions about Intel's compiler and other general rudeness.
##
## I developed this hack against this version:
##
## Intel(R) C++ Compiler for 32-bit applications, Version 5.0.1 Build 010730D0
## Copyright (C) 1985-2001 Intel Corporation. All rights reserved.
##
##
## Usage:
## Install the Intel C compiler. Don't download a license!
##
## Make sure to import all of the variables that the compiler
## needs to function (it won't work with vanilla include/libraries)
##
## Enjoy!
##
echo 'break *0x8056451' >
echo "run $*" >>
echo 'jump *0x80567d0' >>
gdb -batch -x
rm
184 square mm die size (prior to Athlon 800)
102 square mm die size (Athlon 800) ... source
Note that this article also states that: Intel has also incorporated a substantial amount of redundant circuitry in the processor, Krewell said. Chipmakers often use redundant circuitry to boost yields. Sometimes, circuits come out scrambled on a finished chip. If the manufacturer has put in two sets of the same circuits, the chip will function properly because it can use the second set.
You could have a dual Pentium machine and not even know it :)
I guess this redundancy is why the chip has gone up 10% in size in the last couple of months ... (see this article) which quotes:
One of the reasons for McKinley's bigger price tag, Krewell said, is that it will cover nearly 440 square millimeters in area--or more than twice that of the Pentium 4.
Here is an excerpt:
And they said zombies weren't real!
I've been waiting and waiting for a 64 bit processor in my desktop forever. You just can't get all hot and bothered about the itanium till you can have one at home to play with. I'm ready for a massive performance increase in my home computer like we had when the first Pentium came out. More clock cycles are nice but 64 bits get you even more bang for your buck.
If your not cheating your not trying. If your not trying your not winning and if your not winning why play?
Anyon know how much this will cost? Thanks...
PayPal $$ if you sign up for free offers (eBay, cred cards, e
I wonder if AMD will start some sort of "size isn't everything" initiative.
Maybe they could offer some sort of conversion system, so that consumers can easily convert between centimeters and inches, and understand that AMD's new 1.5"+ chips perform about the same as Intel's 20mm McKinleys...
it's how well you use it that's important.
Two things effect die size.
1) "Active Area" is where the Transisters and routs go
2) Bonding Pads. Any chip has to have pads as connection points. As bus widths go up so do the number of I/O pads. Even with inovative connection methods I/O takes up alot of real estate. The good news is that the features of I/O are large so they seldom are the cause of a bad chip so they are less often the reason of a chip process falure. One thing to keep in mind is that Pads must be of a minimum size and must be on teh outsde edge of the chip so that in a wide, but simple chip you can end up with "circled wagons" with a lot of empty space inside.
-s
Does this 3Meg leve 3 cache seem a bit excessive to any one else just to prop up Intel's CISC based arcitecture?...These guys really need to catch up to the rest of the industry go RISC and drop the backwards compatibility.... IMHO It would be a great boon for everyone involved.
Three obvious points:
- The size quoted is die area, not package size. As the article says it IS very, very big.
- This processor is not aimed at the consumer market (ie. it is not intended to replace whatever you have in your machine). The price and production volumes reflect this.
- CPI ([clock] cycles per instruction) is just as important as clock frequency. And to a limited extent so is the instruction set architecture, cache sizes, branch prediction mechanism, datapath width (the number of bits), data bus width, external bus architecture and a whole load of other stuff. Trust that Intel have done their maths and have produced a product that will provide the performance required for the target market.
I fear Slashdot is rapidly becoming infamous not just for high server loads, but for somewhat uninformed "but can you run Linux on it?" style postings.
(Please note, I have no objection to people actually asking "can you run Linux on it?" - just people making uninformed comments)
John
Owl tried to think of something wise to say, but couldn't.
How much of news.com is still owned by Intel? Intel makes the second biggest chip is news? derick
The question with an L1 cache of that size is how many cycles it takes to access the cache. It's easy to make a huge L1 cache, you just pay in increased access time. It's not impressive until we know the latency numbers as well as the size.
Is that an Itanium in your pocket, or are you just glad to see me?
Once upon a mid-day dreary, while I plodded, weak and weary,
Through an informative article about a truly massive core,
While I nodded, the newsfeed was slashdotted, suddenly there came a tapping,
As if FedEx gently rapping, rapping at my chamber door,
"Prob'ly FedEx," I muttered, "with boxes of reminders;
reminders of the law of Gordon Moore."
A feeling of having made the same mistake before: Deja Foobar
Why not just follow IBM and build a good old fashioned Risc chip like the Power4. No instead they decide to build this uberweird VLIW chip with a new name and marketing spin. It is never a good idea to make a product out of research project. Hell they could have purchased the HP-PA Risc or Compaq alpha assets, used the Instruction Set and build an uberfast Risc chip besting their competition in a shorter period of time and continued research using the money spent on Itanium. It is just a crazy processor with too many registers and oversimplified instructions to the point where they have become complex. Hell if amd was to start from scratch they could have just ripped the microOps off of the Athalon used a new instruction set and had a faster chip than the itanium. Intel is trying to make too large of a step too fast. As for 64 bits, who cares except for servers for floating point intel, amd, and the PPC all use an 80 bit mantessa effectively allowing for greater than 64bit fp math and inter math above 32 bits is not very common. The only reason for the 64 bit chips is 64 bit addressing making large ram access possible and also increasing the rate instructions can be sent to the fp units as they are only sent half at a time due to 32 bit memory addressing.
Go to your BIOS and disable the L2 system cache. See how long it takes your computer to boot. :) About 95% the system will read from the chache and not the main memory. This is why it is so important.
But there are segments of today's market that are willing to pay almost any price for a high-performance chip. These people will fork over a $1000 without blinking an eye if they think it will speed up their business.
Look at any commercial server available today. They're priced around $15000 - $20000. If chip prices go to $1000 instead of the $400 they're probably paying, that makes a difference of $2400, or about 12%, in a 4 way box. Even if chip prices went to $2000, it's a $5600 difference, or a 28% difference. If your processors are your bottleneck, then you've gained a lot of improvement for not-very-much delta in money.
Sure, a $2000 chip is out of reach for most home users today, but there is always a market for just about anything faster they can produce.
And there are enough crazed overclockers out there that'll spend whatever it takes to raise their frame rates on Quake III. It'll sell. It'll also drive the market to a new standard, which also sells chips.
John
what's your point?
T Money
World Domination with a plastic spoon since 1984
Funny but Word on my machine, when opening a fairly long document full of tables, with all features turned on, uses 18MB. Sounds like you're a `redicilious' liar.
Someone should inform Intel that President McKinley was assassinated. Will the Hammer do the same to this McKinley?
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer
pleez subscribe me to yoor news leter
of a Beowulf cluster of these guys...
Oh, go ahead. Mod me down. You know you want to.
Michael-
You catch enchiladas by picking them up behind the head and holding them underwater until they don't kick anymore -VeGas
It's really spelled Shavano, not Chivano. In the recent tradition of naming parts after mountain peaks.
never seen the die size, but the final product is half a metre per side and needs a special jig (not to mention 2 days training) to install.
Don't want any bent pins on those suckers!
Most people judge the 'bitness' of a processor by the width of it's memory addressability. I doubt your calc can address 2^64 bytes of RAM.
And by your irrational logic, the Pentium is an 80 bit processor since that is the precision in the x87 FPU.
The latency is no secret. It is a 2 cycle latency cache. Pseudo 2-way set associative (you can load from an even and an odd row at the same time, but not 2 even or 2 odd)
I agree with this post, i'm at 0, and each time i'm tempted to move back, it's not for long. This is an interesting social experiment on why good is better than bad. At present, good wins.
Microsoft - Where would you like to go today, Maybe Jail?
applause
Eventually you'll have 128MB of DRAM on chip. Why? Because it'd be faster. Closer memory is better.
Having the L3 on chip makes the same amount of sense as having the L2 on chip -- which is to say, lots. First, you can run the L3 at core clock speeds. No external bus is ever going to run as fast as pure silicon. This means that the latency is going to be much lower than for an off-chip L3. This means the average memory access time will be lower, which means better performance. Second, the bandwidth can easily be higher, since you don't have to pay with pins for extra data lines and, again, you're running at core speeds.
For those programs whose working sets fit into this amount of memory, the on-chip L3 is going to blow the doors off an otherwise equal off-chip L3.
The enemies of Democracy are
I think it does run older programs. In a simulation/emulation mode. Don't know much on how it works though...
Anyone remember the old tagline: "486 DX/2 66Mhz... Smell something burning?"
Look at how far we've come... O.o;
What you meant to say (and what the article said), is that 464mm^2 is size of the actual die size of the processor This includes the CPU and the caches. The CPU is a relatively small portion of the processor die, and noting there is 3MB of L3, the total cache may amount to 2/3 of the die size. The square on top of the athlon is also the entire processor die: cpu, caches and all.
Also, L3 cache can never perform "equivalently" to L2 or L1 cache unless it runs at core speed. And I can tell you now, it doesn't -- or they wouldn't need L1 and L2. The L3 cache probably runs at something like 10 access cycles or more. It's not difficult to engineer 10 access cycles into any pipeline -- it's impossible. Which is precisely why it's not L1.
I'm quite sure the engineers at Intel have done their modeling homework and determined that however fast the L4 memory may be, the L3 will improve performance by that much more.
Remember, this processor is not meant to go on you or any other Joe Sixpack's desktop. It is meant to sit inside the workstations on the desks of engineers and in the racks of high-bandwidth servers. These platforms are specifically designed to run hundreds of tasks simultaneously and handle staggeringly high memory bandwidths. It has nothing to do with "complicated instructions." The L3 exists for swapping out large pages of memory in large bursts from a significantly larger sized L4 memory (think on the order of 100's of GB) from L5 memory (local drives and SANs) that has an incomprehendable virtual memory space.
This has absolutely nothing to do with mainstream. I'm quite certain an OS already exists that will run on the platform. An IA-64 Linux is well under way (try http://www.linuxia64.org) and you can bet that Compaq, HP, Dell, and Intel have put a total of more than 100x your lifetime earnings into developing software for that platform.
Intel could not care less whether you or 99.9% of the /. readers out there ever buy an IA-64. They don't give a crap about your market segment, but I'm sure if you want to drop $10K+ on a IA64 workstation, be my guest. Your choices are limited. Either choose IA64 or UltraSparc. Or maybe if AMD ever gets a design win, you might get a chance to buy a Hammer box.
Actually, the itaniums which have been shipped so far are a royal pain in terms of power consumption. We have a bunch of them here at our lab and it's crazy - you can not even connect two machines to the same outlet without causing a power failure. I think especially for servers, the time has come where one needs to worry about power consumption; the current itaniums are simply not good enough in terms of effective computing cycles/power. High technology and state of the art should not only be a synonym for "fancy new architecture" but also for "energy efficiency" and "friendly to the enviroment".
i was surprised by the size of my socket 478 p4 i bought a few months ago, but that was b/c it was so small. it was smaller than the p200mmx it was replacing!
:)
btw if anyone is looking for a good DDR board for a p4 and don't wanna pay alot (sub 100) then I recommend the ECS P4S5A. Toms Hardware had a happy review and I'd have to say I agree with everything they said. (But you'll have to dig for it yourself
It's not an overclockers board but I just wanted a good stable board which it is. it uses the SiS 645 chipset as the northbridge and a VIA chipset for the southbridge.
snoogins
No sig for you!!
Bah, I'm at negative K anyway...
"Yes, it LOOKS powerful. Don't touch it. But I predict within the next hundred years computers will be almost TWICE as powerful, one hundred times larger, and SO expensive that only the five richest kings of Europe will own one."
To paraphrase Prof Frink.
Seriously though. Aren't computers supposed to be getting SMALLER, not collos-o-big? Or do I suffer from Slashdotter's Lament (aka, not reading the fucking article before posting something "witty")?
Why is it when I hit ^R that ZSH calls me a cocksucker?
The whole article about "Chivano" and the "alpha concepts" is bogus. Some of the worst reporting I've ever seen. There's a previous post on the correct spelling of "Chivano". Evidently someone overheard a conversation about "Chivano" and it got relayed to a news.com reporting monkey. news.com, you suck.
I've never been able to figure that out.
Is the size of the chip big compared
to non intel processors? The
processors in my indigo2 and my
HP C-180 "appear" to be quite
large externally.
Not only that, I think this thing will run pretty hot...it does have lots of surface area for contact with a cooler, but man, so much circuitry has got to be a furnace...
Perhaps recent AMD developments is making Intel think that heat=performance...
I don't think I ever benchmarked how much memory nroff was actually using, but our 3B2s had 2MB of RAM and 1.5MIPS and chugged along just fine :-)
"... also announced was the new 'Chicanium', which combines the 200Mnerdz power processing of the Itemium with the sexual prowess, digitally extracted, of a cheap Tijuana hooker and her little brother. Release date, 2002."
(The processor, not her little brother.)
; -- the corruption of government starts with its secrets. a truly free people keep no secrets. --
You're absolutely right. On top of that, the yield is going to be ridiculous. See, a wafer has defects. To get a good approximation, imagine a 6 or 8-inch target on which you shoot darts. The best wafer processes give you about half a dozen defects, and boy are these wafers expensive. Each time you have a defect, the chip that is engraved on this spot will be faulty and be rejected.
You can easily see that for a given defect density, the same wafer will have approximately the same number of bad chips (even if you split hair with the probability of getting two defects tiled by the same chip). With a small die, you can easily squeeze more good chips around defect spots. One more reason why a small die size is key to yield.
So this chip is going to cost a freaking fortune to manufacture, especially with the bleeding edge process they are boasting.
But wait, it does not stop here. 22 x 22 mm chips, huh? Assume that the clock tree (i.e., the tree-like circuit that distributes the clock signal in the chip) has a longest path of 10 mm. That's already the heck of a skew on the signal. And you can easily increase that longest path estimate by 30-50% because signals can't propagate in straigth lines, they have to be routed along structures. This alone guarantees the clock speed will never go as high as competing chip's frequencies.
This is a sheer waste of engineering resources. For a processor, such a size is just not practical.
Conclusion: This thing is a demonstrator. It will never fly. It's not meant to. And even for a demonstrator, it's too bulky.
--
Mad science! Robots! Underwear! Cute girls! Full comic online! http://www.girlgeniusonline.com/
For most people, 64-bit arithmetic isn't critical - most applications don't deal with ints larger than a billion, though us crypto people who do lots of bignum math are happy to get a 4x speedup. Otherwise, the quality of floating point implementations is likely to be more important. So it would be possible to get by with 32-bit arithmetic and 64-bit addresses, like we did with the Motorola 68000's 16-bit-ints and 32-bit registers and addresses - but that was also somewhat tacky, and led to *lots* of bugs in code that assumed ints and pointers were the same size, though perhaps we've evolved enough past K&R C that newer software won't make that mistake as often.
A real problem this time around is that the C language and its relatives really do like 32-bit integers, and many of the Unix system calls also assume 32 bits. If you make the native int/pointer sizes 64 bits, there's a lot of stuff that will probably break. What kind of experience have people had running code on DEC Alphas and other real-64-bit chips?
Bill Stewart
New Fast-Compression-only CPR http://preview.tinyurl.com/dy575ks
TESTIFY!
Of all the media bull I've heard about the 64-Bit Intel/AMD chip, I've yet to hear ONE SINGLE person claim that the new chip will be somehow better than the Alpha.
t ml
Tell you what. Since all the apps need to be fixed (or at least recompiled) to work on 64-bit processors anyhow, why not just go the route of porting everything to the Alpha? We could use this to finally get the hell away from Intel's terrible chipset.
And for all of you that think the Alpha will be dying soon, there are plenty of companies other than Compaq with Alpha products that are far better quality than Intel, and will likely be cheaper as well.
http://www.microway.com/products/ws/alpha_21164.h
Slashdot gets worse every day... Pipedot: News for nerds, without the corporate slant
Next, 3 MB cache sounds nice, but L3? It may be on die, but by that point the clock reduction probably makes it perform equivalently to a 256 k L1 cache, or a 512 or larger L2.
A fundamental rule of building caches is that a larger cache is slower and dissipates more energy per lookup than a smaller cache. This is why multilevel cacheing exists in the first place (otherwise we'd just have a huge L1 cache - and before you mention it, due to architectural sneakiness, HP's giant L1 cache isn't really an L1 cache).
So, you can't just spend the L3 area on making a bigger L2. You'd end up with a slower, hotter L2, which could easily _degrade_ performance.
As long as the L3 cache is faster to access than main memory, it'll be useful for some things. Whether it'll be useful for *most* things is another issue. This depends on the "working set" of the applications you're running (how much memory they repeatedly access). I guess Intel's banking on working sets being larger than most caches.
Another possibility is that they're testing the cache architecture for use in future SMT or CMP designs (both of which would have multiple independent executioin contexts running). If you're running multiple *independent* contexts, the working set grows with the number of contexts.
You can find other compilers for Itanium, check out this. Im sure other universities have research into Itanium compilers that might also surpas intel's compiler.
Sure, intel might comeout with a great new 64bit chip. All i wonder though is: why in the world are they still supporting 20 year old 80x86 technology in their hardware? Would not it be easier to complately redesign the CPU? To make it RISC (which has been proven to work faster and be easier to program at the same time)? I am just tierd of hearing stuff like: 64 bit extensions to the registers, so lets see, not we have EEAX (64bit), its lower half is EAX (32bit), its lower half is AX (16bit), and AX in the end is split into AH and AL (8bit each). I am a ower of 2 Alpha Digital workstations (dont confuse that with Alpha PC), and even though they are only 200MHz each, they still seam to run Tru64 Unix with X and Open Desktop really fast. I believe it is time to drop the 80x86 compatibility and move onto the better RISC. Yes, it would be a big step... all the software would need to be rewriten, or at least recompiled;-) but would not it be worth it? Just look at the G4 PowerMac, doesn't that thing kick ass!!! Less MHz yet much faster.
one more thing... most people will run windows on it anyway, so they only difference you are going to notice it that your machine will simply crash faster;-)
EETimes has a nice article with a good graphic comparing the internal workings of the Itanium vs. McKinley ... a good level of detail: 10 vs. 8 pipeline stages, differing bus widths and speeds, execution units, etc.
The article also talks about other intel innovations disclosed at the International Solid-State Circuits Conference
HIV Crosses Species Barrier... into Muppets
chip will be 464 square millimeters which would make it one of the largest ever produced
464 sq mm? That's too small... chips have to be big and crunchy! mmmmmmm... crunch... crunch... (pieces falling into the keyboard)
I've never seen a good explanation of how Alpha concepts could possibly benefit the IA64 architecture. Usually it's only talk about HyperThreading, which is just Intel marketspeak for SMT (Symmetrical Multi Threading) a feature long ago promised for the Alpha and PowerPC product lines -- and a marginal improvement more related to packaging and manufacturing than an architectural feat.
I fail to see how Alpha could benefit IA64, since the fundamentals underlying the two different architecture are quite opposite -- changing IA64 to be more like Alpha would give us probably a worse Alpha or a not so bad IA64, but would fail to realize Alpha's promise of a clean, balanced architecture, and so would be mediocre compared to PowerPC, perhaps UltraSPARC and probably to what Alpha, PA-RISC and MIPS could have became weren't them orphaned.
In fact, it seems to me that even a hypothetical SMT StrongARM would run faster and cooler than an equivalent cost and size IA64. But that's only my quite uneducated guess.
Leandro Guimarães Faria Corcete DUTRA
DA, DBA, SysAdmin, Data Modeller
GNU Project, Debian GNU/Lin
I want a 20" CPU!
The nanochips are vulnerable to the alfa, beta y gamma nature's radiation.
JCPM.