It blows my mind that people publish such error filled articles. As many have pointed out, they blew the definition of a micron (I suspect they really intended to say a micron is a thousand of a millimeter since most people have a feel for a millimeter and a factor of 1,000), but I have yet to see anyone say that 0.18 micron technology does NOT mean that the transistors are now 0.18 microns apart! Far from it! All that means is that the finest lines they draw are 0.18 microns, when drawn. Usually, only the gate length is this size. I even saw a post that said the wires connecting the transistors were going to be 0.18 microns wide. That would be one of the slowest CPUs ever made since the RC time constant would kill you! If you make it to the metal layer with your wire, it is going to be WAY bigger than the gate width to reduce the resistance. OK, enough of my rambling, just wanted to point out another REALLY STUPID comment from the author who obviously has never dreamed of layout an IC.
(Disclaimer: I have worked for both AMD and Intel, although am not currently employeed by either)
It sure seems to me like this doesn't amount to anything unless they actually try and enforce this license. I agree with everyone else who is saying it is probably a rubber stamp licensing form. The easy thing to do is ignore it. The time to get upset is if they do actually try and enforce this agreement. Of course, someone may have mentioned this in the 50-100 posts that have probably been added since I first hit the reply button.....
Okay, so maybe this is a waste of time, but I haven't really paid much attention to the people at O'Reilly before now, I just knew that they made some pretty darn good books. However, after reading these answers, my respect for them has grown immeasurably! The responses left me with that nice warm feeling that there really are Good People out there. Now, if only that updated NAG would get out so I can buy it!
Also, does anyone have any info on actually processor performance comparisons between a PPC and a Pentium/K7^H^HAthlon? I know there won't be Athlon data yet, but I figure the more exposure they get the better.
92 nm is enormously huge! 250nm devices have typically been modeled with 50-60 A (5-6 nm) thick gate oxides. I have seen many papers discussing the reliability of 1-1.5 nm (1.5 nm seeming to be the magic stopping point from a reliability standpoint) thick oxides. I am not sure how you saw 92 nm GATE oxides in any modern devices, perhaps you were looking at the field ox?
Silicon dioxide (SiO2) is a crystalline structure at the macroscopic level.
But when you look at MOSFET gates, there is no crystral structure to be seen, so their suggestion of using this as a measure doesn't make sense to me. Judging from their numbers, it sounds like they are saying the average "atom" is about 2 Angstroms, so why don't they just say the limit is around 1 nm? (haven't read the link to the true report, still going off the mercury story)
We'd either have to figure out how to grow or place single-crystal layers of silicon on to an outer oxide layer of a chip,
This is a known technology....single-crystal epitaxial growth....hence the name Epi-man. It isn't ready for mass production yet, but it is doing some nice stuff in the labs.
In our group, the main reason 3D is not in use today has more to do with the materials and the thermal cycles required to manufacture a true 3D wafer. Currently, SOI (Silicon On Insulator) is not the technology of choice, but is required (by all that I have seen) to add a 3rd dimension. Remember, each switch needs to be electrcially isolated from the others to some extend. Now, the thermal issue is even more confounding. Once you make your first level of transistors, they will undergo all the following steps of the process, so they will see all the thermal cycles as you make more layers of transistors. This will lead to dopant diffusion, which won't allow the very steep doping profiles required for a well behaved MOSFET. Don't give up hope....we have been able to produce devices on two layers and may be close to adding a third without too much damage to the first, although the first layer may be entirely larger size devices used to drive the smaller guys.
Then we can start to worry about the other issues people have brought up.....
The big problem with GaAs is that it doesn't have a kind native oxide (insulator) like Si does, so those chips probably won't be using MOSFETs, but BJTs instead, and consume power in a big way.
They are talking about the gate insulator, the part that you don't want to have current pass through (but is leaky as could be). Electrons (and holes) will always be the means to convey electrical current, by definition.
I find it interesting that they are basing the thickness on the number of atoms given that the oxide is not a crystalline structure? Also, which atoms are they talking about, the silicon or the oxygen, since both are required to make the insulator....maybe they are talking about consuming 5 layers of silicon during the oxidation?
K6 is a registered name (but not "trademark") with AMD. If you look at any official references to it, it is followed by the circled 'R' (vs. the circled 'tm' for trademarks). I used to know the differences between the 'R' and the 'tm' but my brain is failing me. I believe it has to do with limits of enforcement (ie, related products can't have the same name, but the name can be used for any other purpose).
> AMD and Cyrix (may she rest in peace) have > always had branding problems. The seeming > omnipotence of Intel comes from their incredible > marketing machine. Remember the $100 million > spent on the marketing of the PIII?
Hello? Remember, Intel is the money maker here. Recall how much in profits AMD reported last quarter? A loss of 88 cents/share. It is a BIG deal for them to scrap together the resources to do any sort of marketing, they don't have $100 million dollars to put into marketing, they put the money they have into R&D. Heck, their revenue for the quarter was under $700 million. Personally, I think AMD should be proud that people lose sight of the fact that they are so small compared to Intel, and don't have nearly the level of resources to put on major marketing campaigns. I also think that they are putting their money where it belongs, into R&D.
I should mention that I have worked for AMD (and Intel for that matter), although am not currently employed by them.
I have seen a lot of posts here with people saying you only need to worry about 400 MHz or so based on the CPU speed. If we were dealing with sine wave signals for the CPU clock, that would be true, but we are dealing with gross attempts at square waves, which contain a very wide range of frequencies, as pointed out by Ping1400 in a reply burried down there somewhere, this means that we actually need to worry about frequencies at and over 3 GHz. Of course, we are lucky enough that the core voltage is only 2.2 volts (if that much) so you don't have a huge signal to kill....
Re:What filesystem to put on a 216GB drive?
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Sorry to be picky here, but I assume you want to be able to handle a petabyte drive, a drive with 10^15 bytes or 1e15, not 10e15 (that's 10 PB). I just get bothered when people make that mistake and if you meant 10 PB, sorry for assuming otherwise.
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It blows my mind that people publish such error filled articles. As many have pointed out, they blew the definition of a micron (I suspect they really intended to say a micron is a thousand of a millimeter since most people have a feel for a millimeter and a factor of 1,000), but I have yet to see anyone say that 0.18 micron technology does NOT mean that the transistors are now 0.18 microns apart! Far from it! All that means is that the finest lines they draw are 0.18 microns, when drawn. Usually, only the gate length is this size. I even saw a post that said the wires connecting the transistors were going to be 0.18 microns wide. That would be one of the slowest CPUs ever made since the RC time constant would kill you! If you make it to the metal layer with your wire, it is going to be WAY bigger than the gate width to reduce the resistance. OK, enough of my rambling, just wanted to point out another REALLY STUPID comment from the author who obviously has never dreamed of layout an IC.
(Disclaimer: I have worked for both AMD and Intel, although am not currently employeed by either)
It sure seems to me like this doesn't amount to anything unless they actually try and enforce this license. I agree with everyone else who is saying it is probably a rubber stamp licensing form. The easy thing to do is ignore it. The time to get upset is if they do actually try and enforce this agreement. Of course, someone may have mentioned this in the 50-100 posts that have probably been added since I first hit the reply button.....
Okay, so maybe this is a waste of time, but I haven't really paid much attention to the people at O'Reilly before now, I just knew that they made some pretty darn good books. However, after reading these answers, my respect for them has grown immeasurably! The responses left me with that nice warm feeling that there really are Good People out there. Now, if only that updated NAG would get out so I can buy it!
This answers my question, thank you!
Also, does anyone have any info on actually processor performance comparisons between a PPC and a Pentium/K7^H^HAthlon? I know there won't be Athlon data yet, but I figure the more exposure they get the better.
I thought the whole point of buying Apple computers was the OS, not the hardware? Why would Apple care that there are Linux based PPC systems?
92 nm is enormously huge! 250nm devices have typically been modeled with 50-60 A (5-6 nm) thick gate oxides. I have seen many papers discussing the reliability of 1-1.5 nm (1.5 nm seeming to be the magic stopping point from a reliability standpoint) thick oxides. I am not sure how you saw 92 nm GATE oxides in any modern devices, perhaps you were looking at the field ox?
Silicon dioxide (SiO2) is a crystalline structure at the macroscopic level.
But when you look at MOSFET gates, there is no crystral structure to be seen, so their suggestion of using this as a measure doesn't make sense to me. Judging from their numbers, it sounds like they are saying the average "atom" is about 2 Angstroms, so why don't they just say the limit is around 1 nm? (haven't read the link to the true report, still going off the mercury story)
We'd either have to figure out how to grow or place single-crystal layers of silicon on to an outer oxide layer of a
chip,
This is a known technology....single-crystal epitaxial growth....hence the name Epi-man. It isn't ready for mass production yet, but it is doing some nice stuff in the labs.
In our group, the main reason 3D is not in use today has more to do with the materials and the thermal cycles required to manufacture a true 3D wafer. Currently, SOI (Silicon On Insulator) is not the technology of choice, but is required (by all that I have seen) to add a 3rd dimension. Remember, each switch needs to be electrcially isolated from the others to some extend. Now, the thermal issue is even more confounding. Once you make your first level of transistors, they will undergo all the following steps of the process, so they will see all the thermal cycles as you make more layers of transistors. This will lead to dopant diffusion, which won't allow the very steep doping profiles required for a well behaved MOSFET. Don't give up hope....we have been able to produce devices on two layers and may be close to adding a third without too much damage to the first, although the first layer may be entirely larger size devices used to drive the smaller guys.
Then we can start to worry about the other issues people have brought up.....
The actual switches (the MOSFETs) are all in the same plane, on the surface of the silicon wafer.
The big problem with GaAs is that it doesn't have a kind native oxide (insulator) like Si does, so those chips probably won't be using MOSFETs, but BJTs instead, and consume power in a big way.
They are talking about the gate insulator, the part that you don't want to have current pass through (but is leaky as could be). Electrons (and holes) will always be the means to convey electrical current, by definition.
I find it interesting that they are basing the thickness on the number of atoms given that the oxide is not a crystalline structure? Also, which atoms are they talking about, the silicon or the oxygen, since both are required to make the insulator....maybe they are talking about consuming 5 layers of silicon during the oxidation?
K6 is a registered name (but not "trademark") with AMD. If you look at any official references to it, it is followed by the circled 'R' (vs. the circled 'tm' for trademarks). I used to know the differences between the 'R' and the 'tm' but my brain is failing me. I believe it has to do with limits of enforcement (ie, related products can't have the same name, but the name can be used for any other purpose).
> AMD and Cyrix (may she rest in peace) have
> always had branding problems. The seeming
> omnipotence of Intel comes from their incredible
> marketing machine. Remember the $100 million
> spent on the marketing of the PIII?
Hello? Remember, Intel is the money maker here. Recall how much in profits AMD reported last quarter? A loss of 88 cents/share. It is a BIG deal for them to scrap together the resources to do any sort of marketing, they don't have $100 million dollars to put into marketing, they put the money they have into R&D. Heck, their revenue for the quarter was under $700 million. Personally, I think AMD should be proud that people lose sight of the fact that they are so small compared to Intel, and don't have nearly the level of resources to put on major marketing campaigns. I also think that they are putting their money where it belongs, into R&D.
I should mention that I have worked for AMD (and Intel for that matter), although am not currently employed by them.
I have seen a lot of posts here with people saying you only need to worry about 400 MHz or so based on the CPU speed. If we were dealing with sine wave signals for the CPU clock, that would be true, but we are dealing with gross attempts at square waves, which contain a very wide range of frequencies, as pointed out by Ping1400 in a reply burried down there somewhere, this means that we actually need to worry about frequencies at and over 3 GHz. Of course, we are lucky enough that the core voltage is only 2.2 volts (if that much) so you don't have a huge signal to kill....
Sorry to be picky here, but I assume you want to be able to handle a petabyte drive, a drive with 10^15 bytes or 1e15, not 10e15 (that's 10 PB). I just get bothered when people make that mistake and if you meant 10 PB, sorry for assuming otherwise.