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Bell Labs claims to have found new limit for chip size
Nocturna writes "SiliconValley.com reports scientists at Bell Labs claim to have found a new limit on how small they can make chips, doubling the life left in silicon technology. " Essentially, what Bell Labs is saying that you can't go any smaller then 5 atoms of silicon dioxide at the heart of the machine. As before, they are saying that this the limit-although this time it may veryw ell be true, with current materials.
Oh, yeah -- first post! :)
--Tom
Tom Geller
I remember reading in WIRED (The one with Woz on the cover) that there are some silicon substitutes on the way.
Does anyone know more about this/still have the article?
It's a thankless job, but I've got a lot of Karma to burn off
So what are we gonna do when we finally run out of space? Parallel processors? Are there any articles out there that discuss the possibilities?
I find it interesting that they are basing the thickness on the number of atoms given that the oxide is not a crystalline structure? Also, which atoms are they talking about, the silicon or the oxygen, since both are required to make the insulator....maybe they are talking about consuming 5 layers of silicon during the oxidation?
Did you see that? A 10GHz chip is possible with current technology?
Drool...
It's a thankless job, but I've got a lot of Karma to burn off
Essentially, what Bell Labs is saying that you can't go any smaller then 5 atoms of silicon dioxide at the heart of the machine. As before, they are saying that this the limit-although this time it may veryw ell be true, with current materials.
cpeterso
The big problem with GaAs is that it doesn't have a kind native oxide (insulator) like Si does, so those chips probably won't be using MOSFETs, but BJTs instead, and consume power in a big way.
I believe Bose-Einstein condinsate and light are the theoretical switch technology that will replace silicon
If I remember correctly, GaAs uses MESFETs, in which the gate is laid directly on top of the channel.
Another problem with GaAs is that p-channel devices are horrendously slow (like a factor of ten compared to the n-channel devices -- somebody correct me if I'm wrong). With Si, the p-channel devices are only a third the speed of n-channel devices of the same size.
Perhaps the way to go is to supercool traditional Si technology, thereby increasing the electron/hole speed ceilings (1.0x10e7 cm/s at room temperature). The changes in the fabrication equipment will be significantly cheaper and the current generation of circuit designers would not need to be completely retrained.
That's pretty far off from now, so I wouldn't be too worried about maxing out the mhz. Then again, 640k is all anybody will ever need ;).
On a side note, why don't designers use 3D designs? It just seems like 2D transistor grids aren't the optimum. In 3d, the clock pulse would have a much shorter path to follow, allowing higher clock speeds. Sure, it would take a 100k layer process, but you could get away with a much smaller die size.
--- A Jesus Fish eating a Darwin Fish only proves Darwin's point.
When current flows through a wire, atoms in the wire tend to be dragged along with the current. The current density - current per unit cross-sectional area of the wire - has to be kept below safe limits (dependent on temperature) to prevent this. Faster chips are made by passing the same amount of current through smaller transistors - but this means through smaller wires, too. Electromigration limits how small you can shrink the wires before your chip dies an early death. Copper helps - it is much more resistant to electromigration than aluminum - but it's still a big problem, and will keep getting bigger.
You get capacitive coupling between wires that are close together - signal leaks from one to the other. This is worse for wires that are closer together, and worse for higher frequencies. As chips shrink and are clocked more quickly, capacitive coupling becomes an ever-greater problem. Capacitive coupling also causes signal leakage between the various parts of a transistor, as well as between transistor sources/drains and the substrate (though silicon-on-insulator helps eliminate this last effect).
A chip's total parasitic capacitance doesn't depend that much on the size of its transistors; just on its total area. Charging and discharging this capacitance dissipates a certain amount of energy (dependent on the chip voltage). As chips are clocked more quickly, power dissipation goes up in proportion to the clock speed. Reducing the core voltage helps a bit, but the core voltage must always be considerably higher than the transistor threshold voltage. Silicon-on-insulator lowers the total parasitic capacitance, but only to a certain point. The problem remains.
This list completely ignores fabrication difficulties at finer linewidths, though those look like they're tractable. However, electrical problems will still pose limits to how small you can shrink features on a chip. When exactly these limits will come into play remains to be seen, but they are lurking.
Title says it all.
Pretty small ones, at that.
-- Alastair
IMO, most likely better use of silicon at a fixed feature size. You can improve performance by making transistors with a lower threshold voltage (with better-doped silicon or by using another material). You can also boost performance by tweaking the materials used to reduce parasitic capacitance. You could also start developing true multi-layer chips that have more than one layer of transistors, to keep ramping up density (though cost per transistor will level off very quickly and stay constant). More work could also be put into cooling systems that let you clock chips more quickly without having to worry about electromigration. Several other optimizations are probably possible.
Basically, what will happen is that integrated circuits will become a mature technology. Right now they're still in their rapid development stage (think of it as a really long adolesence
There are two obstacles that I can think of. The first is heat disspiation; heat will have to travel farther through the chip before reaching the surface. This could be ameliorated by putting sheets of thermally conducting material between layers, but this is complicated, and they'd have to be pretty thick (unless they were thermal superconductors; IIRC these exist at room temperature).
The other obstacle is depositing a layer of crystalline silicon to make transistors with. Current wafers are still sliced from single crystals of silicon. However, silicon that is deposited tends to be polycrystalline. This gives it poor electrical properties.
We'd either have to figure out how to grow or place single-crystal layers of silicon on to an outer oxide layer of a chip, or else figure out how to make fast circuitry with polycrystalline silicon.
That having been said, this is an idea that I like very much. It is one of the logical ways of extending chips once linewidth reaches its limits.
http://www.bell-labs.com/news/199 9/june/24/1.html
For more info, of course...
Electromigration is supposedly one of the damaging factors of running a cpu overclocked. The electromigration will shorten the chip's lifespan by making weak spots in the "wires". Cooling of the chip helps make the aluminium less resistive. Does this also lower the amount of electromigration? I believe it does. Perhaps all chips in the future will have to be built like Kryotech's computers.
The truth is more important than the facts.
-Frank Lloyd Wright
> why don't designers use 3D designs?
Because 3d is much, much harder to design. Right now, 2d is relatively easy for a human designer to keep track of, but 3d is very very hard to visualise without severe loss of information.
Additionally, routing software and other tools related to design right now just aren't equipped to deal with especially 3-dimensional designs. Throw a third dimension in and you complicate routing dramatically.
Then there's the problem of heat dissipation. It'll get real hot in the middle of that silicon cube.
i.e. 3d chip designs are doable, yes, but they're so much trouble that most designers/producers don't feel that it's worth it right now. I'm sure we'll get to it eventually when we run out of other options.
---
DNA just wants to be free...
Bell Labs announced not too long ago (I think it was in Dec 1998) that they had figured out how to make a gate-oxide for gallium arsenide transistors, and that their P-type transistors were comparable to their N-type transistors.
I always heard that gallium arsenide 1) used a lot of power (which would be taken care of by the above development, and 2) was really expensive to manufacture (don't know why though).
Heat.
Joe Batt Solid Design
That must mean my house is very low power - it only has 60 Hz of power! How will I be able to power one of these chips if my house doesn't have enough power?
When we say we've doubled the life of silicon technology we have to remember that advancements in this field are made exponentialy. We might have double the potential of the technology but not how long it will be around.
"The difference between genius and stupid is that genius has its limits." -- Unknown
I always heard that gallium arsenide 1) used a lot of power (which would be taken care of by the above development, and 2) was really expensive to manufacture (don't know why though).
IIRC, GaAs is expensive to manufacture because the crystal is so sensitive to impurities; much more so than Si. There was an article in an old magazine (PC Mag, probably) about scientists growing GaAs crystals in space, where it is far cleaner than any clean room on earth.
The structure of an IC is already 3-dimensional with all it's via's, bonds, doping etc....
nosig today
But it's still a primarily 2D-based paradigm. As far as I have seen, all conductive segments are typically perpendicular to what I will call the primary plane. This includes vias. (Then again, I haven't looked at a whole lot of recent chip designs..)
I'll put a little speculation in the collective idea pool: I imagine some use of fractal geometry could be found to deal with the volume/surface area heat conductance problems - if a fractal curve can have infinite length in a finite area then why can't a fractal surface have infinite area in a finite volume? (Of course "infinite" would be an approximation) The one thing I cannot realisitcally guess at is how such a 3 dimensional geometry could be manufactured- nanomachines?
Just my 1c...
The actual switches (the MOSFETs) are all in the same plane, on the surface of the silicon wafer.
Circuits are growing up in addition to out.
Linking together the different layers of circuitry gets to be rather complicated and difficult for the fabbing process to pull off. They do it to a certain extent, but increasing the depth of the process is not generally how a part is expanded.
Of course, your E&M equations become much less fun when you have to let go of your 2D abstraction. Don't understimate this fact.
Silicon Dioxide is a 3-atom molecule, made of
one atom of silicon and two of oxygen. So, are we
allowed 5 of these molecules, or 5/3?
Fractal surfaces are better insulators than flat surfaces, as the roughness impedes the curculation of the coolant. Radiative cooling would also be less effective.
This taken into consideration, a properly sculpted surface might have improved cooling properties, at least under conditions where the coolant was coerced into running through a channel. It may also be necessary to use heat-exchanger techniques, and powered pumps for internal circulation of some high efficiency coolant.
What has REALLY LOW!! viscosity, and yet has thermal dimensional stability and high per/unit thermal absorbtion capability? It would also be good if it were an electrical insulator, was a terrible solvent [i.e., didn't like to dissolve things], and had very low capaticance. I can't think of anything quite like that right now. The best that I've come up with is liquid Nitrogen... but that's not very thermally stable (so although it can be used on the outside of the chip, one wouldn't want to use it on the inside, as one might crack the chip [Yes, some PC boards used it on the inside, but we are talking about a different order of magnitude of dimensions here!]).
I think we've pushed this "anyone can grow up to be president" thing too far.
One of the quotes in the article said that the reason this is good news is because many companies don't want to have to rebuild their factories for new technology. So they are happy that the old technology can still keep going.
My question is: What happens when that limit finally comes? All they are doing is delaying the inevitable.
I am an Aerospace Engineer by trade. A major problem the industry is going through right now is this unwillingness to take risks for new technology. The cost of retooling the plant and pushing new tech is just not good news for stock holders who want daily updates on stock profitability.
Eventually the computer hardware companies will run into the same problem. Delaying the inevitable is only going to make the managers that much more unwilling to find new technology to replace the old.
Now how is that going to affect the computer industry in general? When the Moore's law finally stops working, does that mean people will actually slow down and write software optimized for the hardware available at that time? Isn't one of the biggest problems leading to bloatware the fact that with all this new tech, it doesn't matter if your ware IS bloated?
Or will the death of Moore's law be more dire, and lead to a downward spiral of stocks and profits, leading to the next big financial collapse?
What do you guys think?
Posted by 2B||!2B:
There's an easy way to get around the heat issue: redesign so the heat isn't generated in the first place.
I've seen lectures demonstrating solutions for many of the heat issues. At the University of Utah there are research projects (with a bunch of funding from Intel and IBM, where the results are being targetted at production) which tackle the issue of how to use fully asynchronous circuits within a standard CPU, and how to eliminate the refresh of the entire CPU on each clock cycle. Without getting into the specifics (they're all detailed on their web site), the result is a CPU which uses far less current for the same results, while at least doubling its speed due to the improved performance of the asynchronous algorithms. Anyway, heat will be far less an issue as Intel and others make more use of these techniques. And CPU's will be much more appropriate for portable computers, since the power requirement drops significantly.
http://www.async.elen.utah.edu/
http://www.cs.utah.edu/projects/acs/
They will use quantum processors. They can work faster and use similar materials. You don't have the same problems as electrons(wide wires, electrical interference, etc). You can also use different wavelengths of light to trigger a quantum logic gate. There is also little heat.
You will also move into parallel processing on the chip. Multiple execution paths etc.
We still have a long way to go to get the most out of silicon.
GaAs is also a very brittle material, so you're more or less constrained to 4" wafers. Small wafers -> low volume -> high cost.
not an ac, just don't want my info cached here: Harry McGregor, micros@azstarnet.com
I had a chance about a year ago to take a tour through a GaA fab here in Tucson AZ (a small one for Laser diods). It was a class 1000 and class 10000 clean room, (depending on the area, packaging was class 10000). The lithography room was class 100. We actualy got to handle some test wafers (2" wafers), with about 15 of us on the tour we broke 4 of the wafers (out of five!). OptoPower was using 3" wafers for their diods. These 2" wafers were practice wafers for new fab techs to play with first. All of their wafer moveing was being done by hand at the time.
I could've sworn that quote was by Eisenhower, not Ford.
"If one is really a superior person, the fact is likely to leak out without too much assistance" -- John Andrew Holmes
As you shrink the dimentions of a chip, the parasitic capacitance will likely decrease. If you just had a parallel plate capacitor, the capacitance would be proportional to the ratio of the plate area and their separation. If you scaled every dimention by 1/2, the capacitance would actually reduce by 1/2. This is because the separation would decrease by 1/2, but the area would be 1/4 of the original area.
Now, coupling between wires may increase because they will get closer together, and the "plates" of that parasitic are the sides of the wire and the thickness of that wire will not shrink as much as the distance between them. You can reduce this problem by using chip layout techniques to do this.
Other parasitics inside the transistors will reduce, however. The gate capacitances will decrease because the gate oxide is thinner, but the gate area is even smaller. All of the junction capacitances inside the MOSFET channel will also be smaller due to the smaller dimensions.
Matt
anyone, there is such a thing as a thermal superconductor??
With the death of SDI (starwars) came the death of
reaserch into carbon semiconductors. What company
is willing to play with diamond waffers when
benifits might be a decade away? Stock holders
would not tolerate it.
Opticom is a Norwegian based company developing unique all-organic and hybrid silicon/organic memory. They have a working prototype of a 1 Gb 62ns ROM chip. They use a hybrid design combining silicon driver circuitry and Opticoms ROM film. The ROM chips demonstrated the feasibility of multiple memory layers (2-6 layers).
If the semiconductor CPU hits the speed bump, there'll be one rather wrenching consequence: it'll throw off backward compatibility.
No matter what the chip technology used today, the underlying architechture is pretty similar, and this has resulted in a highly interlinked supportive infrastructure - not only do apps stay backward compatible, but algorithms, programs, technogies (and even technologists) continue to feed off of past groundwork.
However, quantum computing involves an entirely different form of math/algorithmic processing which is radically different from that of today's architechture. For instance, unlike sequentially forking down if/else paths, quantum machines simultaneously arrive at all solutions, which requires a different way of programming them.
If the software/logic/algorithms to run on quantum machines is unable to be backward compatible with present computers, it creates a huge gaping chasm between the two.
The consequences should be interesting.
L.
If the 5 atom rule is true for silicon, is this also true for geranium? A more interesting issues, because IBM is sitting on some vary interesting Geranium technology... it will be putting in cell phones... The 10ghz may seem high but 50ghz is the outside limit of Geranium, and I am guessing here, that was based on a 25 atom limit, thus all I wondering is, dose that put Geranium now at 200 to 400ghz? Any Ideas?
Let me ask my question here. Doses the 5 atom Rule apply to gallium Arsenide? If so what is the outside speed limits given what we know?
Actually, limits are track *width* not *depth* which is what's being discussed here. Using photographic techniques or even elecron beams to transcribe a mask onto the surface of a substrate prior to etching is limited by the "wavelength" [any wave/particle dualists out there?] of the transmission. Current 13 micron limits used today refer to this track width.
And it's true from a previous comment that electromigration is a big problem. It happens in the semiconductor as well as the connecting wires.
And there's an even bigger issue. Solid state diffusion. This is what really kills a chip when it runs hot for too long. Atoms migrate [diffuse] within the crystal lattice and boundries between layers get "fuzzy". Ultimately tracks lose integrity and the circuit is broken. Many manufacurers actually factor this and electromigration into their lifetime calculations and have actually been known [!] to build in failure times into their product using these effects. Kind of makes you want to power-down occasionally.
then != than
Numerous other glitches exist in today's stuff, which even a single proofread should be enough to find.
The topic speaks for itself. This really doesn't surprise me, Moore's Law won't just suddenly run out..
I can imagine back in the days of Vacum Tubes that people didn't expect to come up with a new neat way to shrink technology.. Not until it happened anyway.
The lesson to be learned? Expect great things from technology. Don't bet on anything. Expect limits to be broken or avoided.
I just hope that with an advance like this that we won't stop looking into the next generation of computing (Quantum)
Top-of-the line computers currently sport chips with 600 megahertz of power. Timp said a chip with the smallest features possible would allow for computer processing of at least 10,000 MHz.
....
assuming doubling of power every 18months (1.5 yrs)
1.5 yrs 1200Hz
3.0 yrs 2400Hz
4.5 yrs 4800Hz
6.0 yrs 9600Hz
7.5 yrs 19200Hz
time for chip 19200Mhz is 7.5yrs from this year?
peterrenshaw ~ Another Scrappy Startup
I agree :( "Gallium"
Before any of you pull out your AFMs and start building these things, remember that thermodynamics is going to make life really hard on you, unless you can erect massive diffusion barriers (never mind electromigration, the "wires" will interdiffuse unless you keep the stuff real cold).
All you need are a few atoms to migrate in your 5 atom width device and voila, no more device. Migration barriers for self diffusion in Si tend to be only a few eV high at most (some barriers are around 1 eV if my memory serves me). The atoms will sample these barriers around 10**12 1/s, so it is quite likely that at room temperature you will see effects in a short period of time.
Does anyone remember the threading defects in blue solid state lasers when they first came out? They would work for only a few seconds, and then die from thermodynamic driven diffusion, threading defects (basically releaving strain in the lattice by displacing a line of atoms).
I suspect the 5 atom problems will be harder to overcome.
i didnt know moores law applied to clock speed?
besides Kryotech will sell a 1,000 MHz K7 this year and Intel has a 3,000 MHz chip (Deerfield)planned for two years from now.
the discussion is about the future of semiconductor materials, not the future of architechture philosophy. quantum processors made on silicon will run into the same problems!
I wouldn't notice with a thousand proofreads. I :-) I haven't had anyone not understand me yet.
don't know when to use than so I always use then.
A fractal infinite surface in a finite volume wouldn't help cooling your 3D-chip. Because heat would then radiate in this finite volume. The only way to make the infinite surface is by folding it. So most of the radiation from this infinite surface would just hit another part of the surface. With this happening on a small enough scale you effectively have a solid.
I don't think cooling will be a problem though. Tiny pipes through the 3D chip and liquid cooling in the chip will easily give the same level of cooling per transistor as a 2D design. Every pc will come with a cooling unit - so what. They won't get that much bigger.
Even if quantum computing can ever be made to work (meaning Shor-style computation - the way computers work today already depends on quantum effects) it is far too specialised to be useful for general purpose computation.
The successor I've seen for electrical computing is fully-optical computing. Lasers carry your signals, optical gates switch them. You can cross signals over without interference, and the theoretical limits on gate performance and size are ludicrously high. Sorry, no URL - I saw it at a lecture about, uh, fifteen years ago. But I know it's still an area of active research.
--
Employ me! Unix,Linux,crypto/security,Perl,C/C++,distance work. Edinburgh UK.
Xenu loves you!
I have looked at a lot of gate-oxides on semi-current CPU's (most recent was the ppc750), and the smallest gate oxide I have ever seen was about 92 nanometers in thickness. That is roughly 920 atoms thick.
2.5 nanometers is about the limit of a resolvable object on our SEM.
Plus what are they talking about 5 atoms thick? not all atoms are the same size, and Silicon Dioxide is 3 atoms per molecule right? so wouldn't the limit be 6 atoms?
--Bricktoad
My friends, we are nothing but wings on the chicken of society.
That was truly a great post. I am still laughing!
My friends, we are nothing but wings on the chicken of society.
no text
My friends, we are nothing but wings on the chicken of society.
I've seen lectures demonstrating solutions for many of the heat issues. At the University of Utah there are research projects (with a bunch of funding from Intel and IBM, where the results are being targetted at production) which tackle the issue of how to use fully asynchronous circuits within a standard CPU, and how to eliminate the refresh of the entire CPU on each clock cycle.
This does indeed help - however, not that much on a well-designed chip.
A lot of the focus of chip optimization nowadays has been on improving scheduling techniques to let programs take full advantage of all of the chip's facilities at any given time. The eventual goal is that if the chip has two FPUs and three integer arithmetic units, it will be performing two FP calculations and three integer calculations per clock, with no units sitting idle. Asynchronous chips give you a large power savings when you _do_ have chip components sitting idle - you are no longer clocking a module that isn't being used. However, for a chip that is using all parts of itself, all components _have_ to be clocked, which limits the savings that you get from making a chip asynchronous.
It's still a worthwhile optimization; it just won't save you from heat problems as clock speeds rise.
A relatively unexplored area considering it's complexity.
Certainly, human brain cells are relatively huge (and really watery).
I'm not talking physical media, but rather transmission speed/method.
(i.e. as exemplified in neurotransmission.)
Anyone out there with some relevant info ?