Your RCed wrong. The latest version (ultrasparc IV) is a 2 core processor (the two cores being the same as the ultrasparc III) and can run 2 threads (one per core) from http://www.sun.com/processors/. But they are talking about their next generation (which is not ultrasparc) called Rock and Niagara which are supposed to have more than two cores per processor.
Some of what you are talking about like having "virtual registers" are already being implemented by techniques like register renaming where the registers visible to a program are less than the actual set of registers on the CPU. This is useful for things like function calls which involve saving the register states, but could also be useful for multiple threads on the same core.
IIRC, AMD licensed the Alpha memory bus design and it's still used today. It's how AMD ended up with such a fast bus and beat Intel for ~2 years with a faster FSB.
No they do not. AMD used the EV6 bus in the K6-K7 processors. But the current AMD chips uses Hypertransport which was developed primarily by AMD and an on-chip memory controller. In fact, there used to be an independent group that included AMD, Samsung (and Compaq) that was promoting the EV6 bus and the Alpha ISA, but they switched to promoting the hypertransport after Compaq killed the project.
There are still a number of contracts esp. with the DoD (and a few with the French & Australian military too IIRC) that Compaq had signed that would use these machines. Don't forget that the number 3 supercomputer in the Top500 is still a Alpha machine. There are probably a number of applications in that arena that would cost more to port than simply upgrading to these machines.
have not been solved. One type of logic found in computers is called CMOS, the other called TTL. TTL has another special implementation that allows it to achieve high clock rates.
What are you talking about ? TTL is a bipolar logic family and has a handful (10-20) gates (NAND/NOR/INVERT) per chip. Each and every microprocessor or ASIC today uses the CMOS logic. And even though some folks are running around talking about the end of CMOS, these folks don't seem think so. They say we can go on till 2018 drawing gate lengths as small as 22nm (or 18nm effective) (Page 15 in the executive summary PDF) since just about everybody in the semiconductor industry is involved in coming up with this roadmap, I think it just be have some validity...
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Not to mention, the imac uses DDR2 and PCI-Express X800 ATI graphics with 128MB ... a significant update from before
Your RCed wrong. The latest version (ultrasparc IV) is a 2 core processor (the two cores being the same as the ultrasparc III) and can run 2 threads (one per core) from http://www.sun.com/processors/. But they are talking about their next generation (which is not ultrasparc) called Rock and Niagara which are supposed to have more than two cores per processor. Some of what you are talking about like having "virtual registers" are already being implemented by techniques like register renaming where the registers visible to a program are less than the actual set of registers on the CPU. This is useful for things like function calls which involve saving the register states, but could also be useful for multiple threads on the same core.
Yes and all the folks IBM is paying work on the Linux Kernel (or gcc or eclipse) are all being paid by whom ?
IIRC, AMD licensed the Alpha memory bus design and it's still used today. It's how AMD ended up with such a fast bus and beat Intel for ~2 years with a faster FSB.
No they do not. AMD used the EV6 bus in the K6-K7 processors. But the current AMD chips uses Hypertransport which was developed primarily by AMD and an on-chip memory controller. In fact, there used to be an independent group that included AMD, Samsung (and Compaq) that was promoting the EV6 bus and the Alpha ISA, but they switched to promoting the hypertransport after Compaq killed the project.
There are still a number of contracts esp. with the DoD (and a few with the French & Australian military too IIRC) that Compaq had signed that would use these machines. Don't forget that the number 3 supercomputer in the Top500 is still a Alpha machine. There are probably a number of applications in that arena that would cost more to port than simply upgrading to these machines.
have not been solved. One type of logic found in computers is called CMOS, the other called TTL. TTL has another special implementation that allows it to achieve high clock rates. ...
What are you talking about ? TTL is a bipolar logic family and has a handful (10-20) gates (NAND/NOR/INVERT) per chip. Each and every microprocessor or ASIC today uses the CMOS logic. And even though some folks are running around talking about the end of CMOS, these folks don't seem think so. They say we can go on till 2018 drawing gate lengths as small as 22nm (or 18nm effective) (Page 15 in the executive summary PDF) since just about everybody in the semiconductor industry is involved in coming up with this roadmap, I think it just be have some validity
Sure they do. Its called a library.