Not necessarily a spammer. When my company ordered my home cable connection (a nice bennie but it makes me work too much, which I guess was the idea) they had someone else open the account. From talking with her, it seemed like she opened 20 more accounts a day with various ISPs and companies.
IBM is already seriously in bed with SUN: they fab most of SUN's serious chips, including CPUs and are key to SUN's success. So IBM has a heck of a lot of visibility into SUN's future prospects and can make an educated guess on whether or not they want to acquire SUN.
Remember Cyrix? IBM used to fab their chips and there was some speculation on whether IBM would buy them and come into the x86 market. But IBM had visibility into Cyrix's future *and* visibility into AMD's. So was it a good decision to pass on buying Cyrix? I think so.
My point is that IBM could buy SUN if they wanted and if they thought it would be helpful to them. But my view is that IBM is deemphasizing hardware and investing in services, so it's unlikely they'll drop the cash into buying a hardware company.
Careful. Read the article. It won't be a part of most computers anytime soon but people are presently designing with the technology. Without any serious delays you should products coming out in less than a couple of years. It's not much of tweak over SiGe7HP so the real question is if there will be enough of a demand for SiGe8HP. My guess is that there will some demand in the optical communications branch (OC768 and 40 Gb/s communications aren't too far off) and some in low power RF ICs but those aren't huge markets and the price of SiGe8HP may be too high for much acceptance, at least if IBM's history is factored into this.
It isn't the number of transistors that's a problem (when I was there we could easily do tens of thousands). The real problem is getting power into and out of the circuits. The size of the wires to get that much current into BJTs that small is disproportionate and that's the real integration limiter.
Blah, I should know better than to do this so early in the morning. Make that 25.7 Gb/in^2. Sheesh. Gotta get used to these marketing units when talking publicly.
We've already announced the first product to use this technology: the new Travelstars use it to get 25.7 GB/cm^2. Check out the annoucement here or off the IBM home page.
I believe that he's rather understating the problem: in CPUs the clock is the source of major headaches. I suggest you look at any of the recent ISSCC digests to see the lengths to which we have to go to design clocks for these beasts. You'll see H-trees to manage power distribution effectively. You'll see 43 different clock domains with custom alignment circuitry available on test points to accurately align clocks (as the Intel P4 does). You'll see arrays of PLLs in clock subdomains to align clocks and minimize clock skew across the chip (as the IBM POWER3 does). To say that clock distribution is a major headache is an understatement; and he does underestimate the amount of power that the clock tree consumes since can be higher than half the chip power in some MPUs. The numbers he gave are appropriate for a normal ASIC, not a CPU.
All that said, async circuits have been around a long time and they have yet to prove viable. The overhead for adding the additional "computation completed" signal usually more than compensates for area and speed savings you might get for getting rid of the clock. Besides, you still have to clock the output to be able to talk to any modern bus. I'll believe this when I see the details of the "new magic" in operation, but right now I put this in the same class as "cold fusion."
I'll come at this from a slightly different point of view. I've been a Ph.D. EE specializing in very high speed analog ICs for a major semiconductor vendor for a while. From time to time I'll get out and see how the market is and do some interviews. I can honestly say that I think my Ph.D. has caused me a fair number of problems from managers who tend to think that just because I have a Ph.D. I don't want to or can't do practical circuits. I have been to several companies where I have been directly challenged on working in a non-ivory tower environment with a Ph.D. Not all managers feel this way, but enough do to be surprising and annoying to me.
Besides, the best economic return for an EE comes with an MS if you work out the numbers and lost opportunity cost. The only way a Ph.D. works out is if you really value education, really enjoy what you're doing, or need it to get through various artificial government requirements for getting a job in this country.
It isn't all that new. It's an evolving field that Carver Mead basically started back in the 80s that's slowly been building steam. The problem is that while the cost for neurons in biology is very low, that's not the case in silicon, so building large scale systems is problematic. Further, the compuations tend to be analog in nature, so you have to take care how you design the cirucits. Still, the area is a neat thing to watch evolve.
The linux types around here should like the approach they take: free tools they wrote (and distribute) that run under linux. Try http://www.pcmp.caltech.edu for the details on their work.
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Not necessarily a spammer. When my company ordered my home cable connection (a nice bennie but it makes me work too much, which I guess was the idea) they had someone else open the account. From talking with her, it seemed like she opened 20 more accounts a day with various ISPs and companies.
IBM is already seriously in bed with SUN: they fab most of SUN's serious chips, including CPUs and are key to SUN's success. So IBM has a heck of a lot of visibility into SUN's future prospects and can make an educated guess on whether or not they want to acquire SUN.
Remember Cyrix? IBM used to fab their chips and there was some speculation on whether IBM would buy them and come into the x86 market. But IBM had visibility into Cyrix's future *and* visibility into AMD's. So was it a good decision to pass on buying Cyrix? I think so.
My point is that IBM could buy SUN if they wanted and if they thought it would be helpful to them. But my view is that IBM is deemphasizing hardware and investing in services, so it's unlikely they'll drop the cash into buying a hardware company.
Careful. Read the article. It won't be a part of most computers anytime soon but people are presently designing with the technology. Without any serious delays you should products coming out in less than a couple of years. It's not much of tweak over SiGe7HP so the real question is if there will be enough of a demand for SiGe8HP. My guess is that there will some demand in the optical communications branch (OC768 and 40 Gb/s communications aren't too far off) and some in low power RF ICs but those aren't huge markets and the price of SiGe8HP may be too high for much acceptance, at least if IBM's history is factored into this.
It isn't the number of transistors that's a problem (when I was there we could easily do tens of thousands). The real problem is getting power into and out of the circuits. The size of the wires to get that much current into BJTs that small is disproportionate and that's the real integration limiter.
Blah, I should know better than to do this so early in the morning. Make that 25.7 Gb/in^2. Sheesh. Gotta get used to these marketing units when talking publicly.
We've already announced the first product to use this technology: the new Travelstars use it to get 25.7 GB/cm^2. Check out the annoucement here or off the IBM home page.
I believe that he's rather understating the problem: in CPUs the clock is the source of major headaches. I suggest you look at any of the recent ISSCC digests to see the lengths to which we have to go to design clocks for these beasts. You'll see H-trees to manage power distribution effectively. You'll see 43 different clock domains with custom alignment circuitry available on test points to accurately align clocks (as the Intel P4 does). You'll see arrays of PLLs in clock subdomains to align clocks and minimize clock skew across the chip (as the IBM POWER3 does). To say that clock distribution is a major headache is an understatement; and he does underestimate the amount of power that the clock tree consumes since can be higher than half the chip power in some MPUs. The numbers he gave are appropriate for a normal ASIC, not a CPU.
All that said, async circuits have been around a long time and they have yet to prove viable. The overhead for adding the additional "computation completed" signal usually more than compensates for area and speed savings you might get for getting rid of the clock. Besides, you still have to clock the output to be able to talk to any modern bus. I'll believe this when I see the details of the "new magic" in operation, but right now I put this in the same class as "cold fusion."
I'll come at this from a slightly different point of view. I've been a Ph.D. EE specializing in very high speed analog ICs for a major semiconductor vendor for a while. From time to time I'll get out and see how the market is and do some interviews. I can honestly say that I think my Ph.D. has caused me a fair number of problems from managers who tend to think that just because I have a Ph.D. I don't want to or can't do practical circuits. I have been to several companies where I have been directly challenged on working in a non-ivory tower environment with a Ph.D. Not all managers feel this way, but enough do to be surprising and annoying to me.
Besides, the best economic return for an EE comes with an MS if you work out the numbers and lost opportunity cost. The only way a Ph.D. works out is if you really value education, really enjoy what you're doing, or need it to get through various artificial government requirements for getting a job in this country.
It isn't all that new. It's an evolving field that Carver Mead basically started back in the 80s that's slowly been building steam. The problem is that while the cost for neurons in biology is very low, that's not the case in silicon, so building large scale systems is problematic. Further, the compuations tend to be analog in nature, so you have to take care how you design the cirucits. Still, the area is a neat thing to watch evolve.
The linux types around here should like the approach they take: free tools they wrote (and distribute) that run under linux. Try http://www.pcmp.caltech.edu for the details on their work.