Actually the first 3D processor, (which we built, came out of fab Nov 2004) put the memory above the processor. It allowed a much higher bandwidth to the CPU than going through normal I/O. It has 40,000 interconnects between the memory and the cpu, (although many aren't used for signals).
You are right, but wires are the primary source of the capacitance.
FYI the leakage is the result of the very thin glass between the gate and the substrate. (@90nm gate oxide is about 15 angstroms) This leakage is the same as the tunneling which is done to program flash or EEPROM. Of course, in flash or EEPROM you only provide the programming voltage for milliseconds, not forever.
Heat is not a fundemental issue for 3D circuits. The biggest problem in general is not moving the heat from the transistors, where it is generated, to the silicon, or even from the silicon to the package. Its moving the heat through the package. Same problem in 2D and 3D.
Designer of 3D ICs.....
There are no commercial ICs which have multiple layers of normal transistors on a single substrate. A few companies have worked in this area and current Standford has a DARPA program to try to produce more than one layer. The issue is it requires a very high temperature to produce the high quality oxide the insulates the gate from the substrate for a transistor. This temperature causes issues for interconnect metals and for dopent migration in previous laid down. People have built thin film or polysilicon transistors on top on normal high performance transistors. This is done in large low power static RAMs. But thin film or polysilicon transistors are ~10,000 times slower and are very weak. In the SRAMs there only used as pullups. Dr Lui is building multiple layers on normal, high speed silicon transistors. My company has done the same with a different technique. Right now, we have some of the worlds only 3D ICs. And the only real near production parts.
Data points.
3D devices have been created already, as we have done it. Processors and memory, FPGAs, CMOS sensors... And these are truely 3D. They started life as seperate 8" wafers. The interconnect is through the wafer and we can have as many as 450K per sqmm. Each additional layer adds ~12um.
The problem with heat is no worse in 3D ICs than in 2D - it also no better. You do get a power benefit from 3D. It can be very significant. All power, except leakage is the result of the switching capacitance of the circuits. About half of the capacitance is in the wiring at 130nm. With each generation the wire capacitance is increasing and this is creating a fundemental speed limit in ICs. ( wires get smaller increasing R and closer together incresing C)
Pads today can be placed anywhere on the die and often are. The chips are then Flip-chipped to a substrate (package) This is typical in most Intel, AMD, IBM, etc processors.
Yield and Cost
Yield is per sqmm, no matter 2D or 3D. If a 100sqmm IC yields %50 in 2D, cutting it into 4 25sqmm chips and stacking them still gives %50 yield. You would however reduce the power or increase the performance depending on the tradeoffs exercised. The cost of stacking wafers is about the same as adding another layer of metal to a wafer
The surface on most wafers below the ~180nm processing node are planarized. Thus the surfaces are typically flat to ~+/-1um across an 8" wafer.
Interconnect below 180nm is almost all copper. This provides lower resistance and works better with the methods to give planar surfaces. In reality, the process for wire is to first put down glass. Then trench into the glass a channel, deposit a barrier to keep the copper from moving around, then deposit copper seed crystals, then lastly plate the copper on to the surface. After this the copper is polished down to the glass surface.
DRAMs and Flash still tend to use only aluminum metal systems even at 90nm.
DRAM often uses 2 polysilicon layers. Flash and EEPROM also. But virtually all other ICs only have a single poly layer. The resistance is ~100x greater than metal.
Regards,
Slashdot Mirror
Actually the first 3D processor, (which we built, came out of fab Nov 2004) put the memory above the processor. It allowed a much higher bandwidth to the CPU than going through normal I/O. It has 40,000 interconnects between the memory and the cpu, (although many aren't used for signals).
You are right, but wires are the primary source of the capacitance.
FYI the leakage is the result of the very thin glass between the gate and the substrate. (@90nm gate oxide is about 15 angstroms) This leakage is the same as the tunneling which is done to program flash or EEPROM. Of course, in flash or EEPROM you only provide the programming voltage for milliseconds, not forever.
Heat is not a fundemental issue for 3D circuits. The biggest problem in general is not moving the heat from the transistors, where it is generated, to the silicon, or even from the silicon to the package. Its moving the heat through the package. Same problem in 2D and 3D. Designer of 3D ICs.....
There are no commercial ICs which have multiple layers of normal transistors on a single substrate. A few companies have worked in this area and current Standford has a DARPA program to try to produce more than one layer. The issue is it requires a very high temperature to produce the high quality oxide the insulates the gate from the substrate for a transistor. This temperature causes issues for interconnect metals and for dopent migration in previous laid down. People have built thin film or polysilicon transistors on top on normal high performance transistors. This is done in large low power static RAMs. But thin film or polysilicon transistors are ~10,000 times slower and are very weak. In the SRAMs there only used as pullups. Dr Lui is building multiple layers on normal, high speed silicon transistors. My company has done the same with a different technique. Right now, we have some of the worlds only 3D ICs. And the only real near production parts.
@90nm Wires are the main source of capacitance. @45nm they will constitute ~80% of the capacitance.
Data points. 3D devices have been created already, as we have done it. Processors and memory, FPGAs, CMOS sensors... And these are truely 3D. They started life as seperate 8" wafers. The interconnect is through the wafer and we can have as many as 450K per sqmm. Each additional layer adds ~12um. The problem with heat is no worse in 3D ICs than in 2D - it also no better. You do get a power benefit from 3D. It can be very significant. All power, except leakage is the result of the switching capacitance of the circuits. About half of the capacitance is in the wiring at 130nm. With each generation the wire capacitance is increasing and this is creating a fundemental speed limit in ICs. ( wires get smaller increasing R and closer together incresing C) Pads today can be placed anywhere on the die and often are. The chips are then Flip-chipped to a substrate (package) This is typical in most Intel, AMD, IBM, etc processors. Yield and Cost Yield is per sqmm, no matter 2D or 3D. If a 100sqmm IC yields %50 in 2D, cutting it into 4 25sqmm chips and stacking them still gives %50 yield. You would however reduce the power or increase the performance depending on the tradeoffs exercised. The cost of stacking wafers is about the same as adding another layer of metal to a wafer The surface on most wafers below the ~180nm processing node are planarized. Thus the surfaces are typically flat to ~+/-1um across an 8" wafer. Interconnect below 180nm is almost all copper. This provides lower resistance and works better with the methods to give planar surfaces. In reality, the process for wire is to first put down glass. Then trench into the glass a channel, deposit a barrier to keep the copper from moving around, then deposit copper seed crystals, then lastly plate the copper on to the surface. After this the copper is polished down to the glass surface. DRAMs and Flash still tend to use only aluminum metal systems even at 90nm. DRAM often uses 2 polysilicon layers. Flash and EEPROM also. But virtually all other ICs only have a single poly layer. The resistance is ~100x greater than metal. Regards,