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Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
More 3d accel??? ;)
Hopefully there will be a parallel advance in cooling technology.
Karma: -2147483648 (Mostly affected by integer overflow)
I think what they mean is that instead of the processor being on a single plane (a silicon wafer) it's on 2 or more wafers (stacked on top of each other or somesuch)
Show this to your friends and family that don't know what a real hacker is
But gamers have known about 3d chips for years..
Flat chips suck. These chips have flavor ridges(tm).
I thought they'd been doing this all along.
Guess I was just ahead of my time...in my head.
We complain about all the /. stories that are dupes but don't give proper credit to the editors when a non-dupe makes it past their radar.
Propz to Timothy for posting an original article! Keep up the good work!
Yay... Technicians already have enough trouble figuring out how to layout 2-D circuit boards. This will just give engineers more work. >_
It all depends on density of the transistors. You can squeeze 1 square mile into a 1 inch cube, but it will take 334,540,800 individual layers to do so.
Want to write a time travel game. Or maybe I already did.
Already been done.
Quick, someone send themselves back in time to blow this guy up.
I read in a paper recently where scientists have had some success in developing a four-dimensional transistor by using nanotubes to set up a quantum Klein bottle wherein the current passes through Bohr space and thus runs parahybolically.
In practice, you should actually be able to use this method to set up any n-dimensional transistor, provided you can find a sufficiently clean source of power. Modern power supplies have heretofore been plagued by an excess of static dissonance.
hahahahaha
concerning heat, it seems like this would create a chip that has more transistors per surface area of the chip. regardless of wire lengths, wouldnt this result in a much larger amount of heat per square cm of chip surface? granted we are talking about traditional cooling methods with one side of the chip exposed and meant for heat dissipation, but i dont see how this answers the problem of thin wires leaking electrons or other quantum issues.
Beware the Jubjub bird, and shun the frumious Bandersnatch.
Essentially, they say this packs it denser. And a cube vs a flat processor = less surface/transistor. I see only factors which makes this *harder* to cool. Maybe someone can explain...
Kjella
Live today, because you never know what tomorrow brings
Six - one on each side?
it's just Rensselaer Polytechnic Institute, not THE RPI . . .
Frito Lay developed the 3d chip a long time ago: Doritos 3D
Oh good, so they figured out how to add the extra dimension into ICs now? I was tired of having my reality compressed onto a 2D plane everytime I wanted to use my computer.
I remember there were tests using diamond deposited on chips as a strong heat conductor. The whole point was to help make multilayered chips possible. Haven't read anything lately but it sounded promising.
Wonder at what stage their research is at ... /results to show ?
have they been able to make actual chips ? any metrics
i guess it would be atleast a decade before it becomes really commercial , getting decent yeilds out of such a complex and radical shift would be a real task.
Been there, done that.
So how does this make the actual fab process "better". I meen as it is their is so much that can go wrong that apples are terrible, intel isn't much better. Hell my old old old old old powerbook still works but somehow by "better" ibook's logic board melted, honest it did.
This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.
This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.
From the article:
Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.
"You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.
Please help metamoderate.
Go git her Donatello!
Where's my free iPod!? Until then, I'll settle for a kiss...
There must be a new meaning of the word "simple" that I'm not familiar with.
Mea navis aericumbens anguillis abundat
With 2D Chips, every part of the chip was very close to the surface. With 3D Chips, parts can be layers away from the outside of the chip, so cooling cannot be done as easy on 3D chips. Does anybody know how they are dealing with these problems?
Duh!
And if the guy at RPI who can pack so many layers onto a chip cannot deal with a slashcrowd, he doesn't pass muster.
See: Thermal Conduction Module: A High-Performance Multilayer Ceramic Package
Chip H.
...a potato?
Jurisprudence Fetishist Gets Off On A Technicality --theonion.com
"We've gone beyond zero insertion force -- you just throw the cubes into the enclosure and they will connect," said an Intel spokesman.
According to the spokesman, the functionality of the system will depend on the orientation of the chips as they land in their respective sockets. If the chips land on 7 or 11, Windows will run; 2, 3, or 12 produces the Blue Screen of Death. Similarly, any other number will produce an exception unless it is thrown again before a 7.
Intel Centumvigintiquinqueium ® Proccesor 6.0 Ghz
RUPERT! I TOLD YOU TO WATCH THE BAGS! You were looking at the boys again, WEREN'T YOU.
... as long as my laptop isn't going to get any thicker.
Time to break out the blue/red glasses!
(ducks)
Because it looked like a chip was coming right at me!
Perhaps the whole package should be made from diamond too.
Why would anyone engrave "Elbereth"?
There are a lot of hurdles that this document doesn't really get into. It does mention manufacturing but here are some hard core items that need to be considered. 1. Yield goes as e^(-alpha * A) where A is your area and alpha is your yield coefficient. So if you have non-yielding chips on one wafer and you mate it to another wafer that also has non-yielding chips, your total yield goes down at somehting like Y^L where L is the number of layers and Y is the yield given above and Y is 1. So if your yield is 75% and you have 5 layers then your final yield will be only 23%. 2. Testing. If a whole wafer is bad and you put it in your stack of chips, all the chip stacks will be bad. It would be best to test before you put those wafers together. Thats not easy. 3. Packaging is a big issue. Will it be standard wire bonding or something else. Does this thing really generate a lot less heat? And are the interconnects really a lot shorter. If the chip to chip connects cost the same as inter die vias then maybe so but my guess is that those chip to chip connections are a lot more expensive and take a lot more area than vias within the same chip. And alignment of one wafer to the next is also an issue along with getting good interconnect all the way through those stacks. Anyway, those are some thoughts. Its clear to me that 3D chips are a long way off and have there place in very specialized applications in the near term due to the complexities mentioned above. Wardini
I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.
Didn't Gene Amdahl blow a fortune trying to do this 20+ years ago? I think the company was Trilogy. They did succeed in some die stacking technology but I think they ended up selling the ideas and it went nowhere.
The math is simple. The dissapation of heat from the chip is directly proporational to the surface area of the chip. A flat square chip of volume v has a *much* larger surface area than a cube of volume v (or the worst case, a sphere of volume v). As their stack gets thicker, the chip will of necessity require more exotic cooling mechanisms to extract heat fast enough to keep it cool. The advantages of 3D design (shorter traces, etc.) are only a Log advantage. The heat dissapation problem rises faster than this.
This is an area that I actually know something about. I have an advanced degree in VLSI circuit design and have studied details of today's IC fabrication process.
First of all, the title is incorrect. RPI hasn't "created" anything. From what I read in the highly theoretical article, the only thing that Lu has done is start a program at RPI to look into stacking wafers. Granted, procuring funding for an IC fabrication research is phenomenal news given the exorbitant cost of the facilities! But this article serves no other purpose than to promote a new VLSI research program.
The concept of stacking ICs vertically is nothing new! The idea has been completely obvious since we started running out of room in the 2-dimensional plane. The root problem, and the one that Lu hopes to solve, is that IC fabrication is a highly complex chemical process. The bare Si wafers go through dozens of processing steps where liquids and gasses are deposited and then removed using masks accurate to the nanometer. Layer upon layer of accurately doped Si is added to yield the perfect consistency of impurities (usually Boron or Phosphorous). This gives the wafer its p-n junctions: the crux of every transistor and active circuit element. Multiple layers of polysilicon (a substitute for metal due to the improved accuracy in placement), and metal (usually alluminum) are used for interconnecting the active and passive devices created in the base silicon. The final layer deposited is a several micron-thick glass that serves to protect the wafer's ICs from any chemicals exposed to the wafer post-manufacturing. This is a severely minimalistic description of how ICs are created, but I think you get the picture of how difficult it is and why it costs so much.
The thing is, after the numerous layers of Si, Al, and SiO2 are deposited, the surface is extremely "rough and bumpy" for lack of a better word.
If you were to place the active regions of more transistors on top of all this stuff, your Xistors are almost guaranteed never to *all* be working. It is extremely difficult to expose the several nanometer wide interconnect from one layer through the glass. On all ICs, this is done on very large metal pads that are on the outer edges of the layout. In order to decrease the path length from one wafer layer to the next, this pad must be somewhere over the circuit, which is currently not feasible!
I'm curious how Lu theorizes he is going to slap 3 glued wafers together while guaranteeing proper interconnections. This is a problem we've been trying to solve for quite some time. Alas, the article doesn't state any of this useful information.
I was excited when I read the title, but this article doesn't deserve the headline on the front page of slashdot, IMHO.
On a less critical note, I'm confident that Lu (or any of the many other semiconductor researchers in the world) will eventually make progress toward 3-dimensional fabrication. Unfortunately, I don't see this happening for at least a decade. Even more unfortunate is that the cost of 3-dimensional stacking won't be cost effective for customers of ICs for quite some time (~20-30 years!). I wish Lu and his competitors all the luck that they'll need in this area.
I am NOT putting my signature in this stupid little box! How do I know you won't steal my identity???
Who here thinks this guy blantantly ripped off the ninja turtles when he created the monkey ninjas cartoon?
http://www.monkeyninjas.com/
No shit, even the intro song is a rip off. Guy needs to get some originallity.
At least not in the USA.
...and I want a good explanation, not one that just says it is so.
I always thought it was the resistance that caused heat and not the current.
Anybody got any links that demonstrate what the correct situation is?
It was in my school and I live in Cobb County, Georgia. Maybe it was because it was an honors course.
I am Spartacus
They've just taken something that we are having a very hard time cooling and reduced the exposed surface area enormously, thereby making it phenomenally harder to cool.
On top of that they've taken the most complex and difficult-to-design systems known to man and made them exponentially more difficult to design.
Oh, and then don't forget that they've also taken the hardest manufacturing process known to man and made it exponentially harder too.
No chance. Shorter wires are easier with different architectures. No need to go 3D for that -- it just makes the routing problem unbelievably harder...
Oh and a quick explanation (sorry, can't find a link, no time) is that resistance restricts the electric current. Less currenct == less heat. Power lines have tons of resistance so lots of power (Watts ... I won't go into detail) can travel through them without them melting. Unfortunately this also means that you as a human have a lot less resistance than the wire so electricity wants to travel though you more than the wire seeing as you are the path of least resistance.
I am Spartacus
Ohm's law. Resistance is the impedance to the passage of current that is motivated by the difference in the electrical potentials of two points. Resistance is a measurement of the obstruction the current encounters in a path that decreases voltage. The waste energy transforms into heat. Consider current as water, resistance as as a series of hills, voltage as the speed of its flow to understand the relations.
It's all interrelated.
.
,Power can also be defined as :
The basic Power equation (in Watts) is Volts times Amps (V*I)
Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).
So substituting back into the original equation
P = (I*R)*I = I^2R
P = V*(V/R) = V^2R
So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.
Has an article on a 3d puter. They seperated the components of a chip into 3 or 4 levels. It had a bus that traveled up through the levels on the sides.
Alot of articles but no production. It's one of the fastest masterials to make transistors.
Sorry, but 3D chips have already been done.
Falun Dafa is good!
wow... that's so wrong.
/. tutorial on power line transmission. For more basic information, along with images, check the howstuffworks article on power distrobution: http://science.howstuffworks.com/power.htm
resistance is like the size of a pipe that water is flowing through, consider voltage like water pressure and the current like the flow of the water. the smaller the pipe is, the more pressure you need to pass the water through at the same speed.
For the next blurb to make sense, I need to say that while transformers step up Voltage, the power calc is the same on both sides of it (V*I on one side == V*I on other side)
Power lines are actually really low impedance (resistance in AC) wires, but due to their astounding length they have pretty high resistance. To reduce power loss in power lines, the electrical companies step up the Voltage using a transformer. They do this because if you up the voltage in the middle step, (the power lines) the loss in power is much less, as the current delivered to the end user is much less than that going through the lines.
Thus ends your
I always thought it was the resistance that caused heat and not the current. Anybody got any links that demonstrate what the correct situation is?
(The following is extremely simplified, and ignores alternating voltages, capacitive and inductive effects).
Two equations:
U = I*R (Ohm's law)
and
E = U*I
E is the heat energy
U is the voltage
I is the current
Now, it depends on your situation. If your power source is constant voltage (or, in more engineering terms, it has low internal resistance, for example mains power), U is pretty much constant. The current through a load is then determined by the resistance of the load (using equation 1). The amount of heat you get is then proportional to the current, and inversely proportional to your resistance. So, if you plug in a heater to the wall, the lower the resistance of the heating coil, the more current flows through the circuit and the more heat energy you get.
A less perfect voltage source (say, a battery) has significant internal resistance; the more current you extract from it, the more its voltage drops. Your first equation becomes U = I*(R+r), with R being the internal resistance of your battery. You'll get most power from this setup when the resistance of your load equals the internal resistance. At this point, the heat generated in the battery is equal to the heat generated in the external load.
And, for fun, you can also build current sources, that force a certain current through any load you connect to them (within limits, of course). They do this by changing their output voltage to match the resistance of the load. There are *many* uses for such sources in electronic devices.
Anyone else?
If we have a solid block chip, it's going to get very hot on the inside. Could they design some kind of fractal chip to create a reasonable trade-off between interconnection and surface space so that we could blow air over more of the chip?
Computers are useless. They can only give you answers.
-- Pablo Picasso
Power is not the same as power dissipation, so no I don't see.
The first two sentences of your post are essentially correct (except for spelling errors). The rest of your post is just so wrong that people who read it should invert everything to get the correct information.
http://www.matrixsemi.com/Matrix has pioneered the 3D manufacturing of ICs using a slightly modified standard process. Currently they make one-time writteable chips with 8 layers of devices (not full fledged transistors). Their product sell as the memory chips for some Mattel titles on their JuiceBox crapola. They are supposed to come with rewrittable chips some time soon which will mean cheaper Flash like memories for cameras and other things.
The power problem is not as big for memories, as for digital chips, if all you do is take the same devices and put them in 3D, the die area and the capacitance of the wires hence the power will be reduced. But if you make a chip of the same size as today, with N-layers more transistors, it will probably dissipane N-times energy and exceed the heat dissipation of heatsinks.
Hence all you can get from this is a cheaper memory/processor, not much improvement in performance
You've missed my point entirely.
You can say E=U*I all you want, but that doesn't demonstrate it so.
It makes more sense to me that the heat given off should equal a percentage of current * resistance, so if that isn't true, I need to know the reasoning behind why that isn't true.
But current should be the speed. Part of the problem with the education process is that they don't use unambiguous terms and then don't fully explain what they actually do mean when they are using a term.
Practically everyone these days are acting like Humpty Dumpty in Alice in Wonderland.
If current is the water then does current = mass? If not then what?
http://stripeys.com/stripey/humptyandalice.htm
Presumably you have been googling for explanations of power and energy to satisfy your curiosity. Find anything yet?
Problem solved!
Those who sacrifice security to condemn liberty deserve to repeat history or something. - Benjamin Santayana
It isn't?
My understanding was: You have a voltage drop across your wire (V) and a current running through the wire (I). The power that the wire is dissipating is then V*I.
That energy is going somewhere and is lost (mostly to heat) so what exactly is the problem here?
So basically, what you're saying are cons are actually pros. You just increased the granularity of the process. The total (unstacked) area of the chips will be relatively the same whether they're laid out flat or stacked, so the odds of the chip having no error in it are the same. However, whereas with current technology, the whole chip would have to be thrown out, in a stacked chip, only the bad layer would have to be remade. This assumes that it is possible to test layers separately. If it is possible, it would be possible to decide whether it would be worth it to remake a layer or not, or even stock layers before assembling them, in order to reduce the number of good chips made useless by bad ones.
If it is too complex/expensive to test separate layers (or separate groups of layers), the yields are still not worse than with a single layer chip of the same surface area.
Try Corewar @ www.koth.org - rec.games.corewar
The next "revolution" (actually, evolution) will probably be in parallel processing.
It's already starting, what with multi-CPU chips, multi-socket boards and all.
(Actually, it's been going on for many years.)
Eventually, each PC will have thousands or millions of CPUs, all working in parallel.
The challenge is in how to get them to communicate efficiently with each other and with shared peripherals.
Will the CPUs be configured as a hypergrid, as some sort of hierarchy, or something else?
Will the CPUs be able to reconfigure themselves dynamically as needed, and, if so, how flexible will this reconfigurabilty be?
How will memory be shared among processors?
Will each CPU have its own local memory, plus some memory that it shares with other CPUs?
Research into these questions, and others, has been going on for years (I read about a lot of this when I was in college in the 1970s), but it's going to get more intense as multi-CPU machines get cheaper and cheaper.
Those who sacrifice security to condemn liberty deserve to repeat history or something. - Benjamin Santayana
I always thought that most of the energy was going wherever the current was, and that only some of it was dissipated as heat and therefore didn't make it to where the current is going.
3-D chips do decreases wire length, according to the thesis and the IEEE paper in the links below, 56% less interconnect is required for a 5 layer chip. Wafer bonding has been thoroughly investigated, and processes compatible with standard CMOS have been found and will soon find a use in memory (I'm sure I read something about a start-up stacking chips for memory, I think it was called Tezzaron).
d csg/publications.html
I EEE.pdf
:-)
http://www-mtl.mit.edu/researchgroups/icsystems/3
http://www.stanford.edu/class/ee311/NOTES/3DProc_
The big problems facing the industry are the lack of good design tools and the issues associated with yield and heat. Design tools will be developed as the processes become more refined. Yield issues and heat will likely need to be taken into consideration in the design. Consider if you have an 80% yield on each wafer; when you have 5 layers of silicon--assuming defects are not correlated to the location on the chip, and no defects due to the bonding process--your yield reduces to 33%. Of course, we are able to have more redundancy with more silicon layers, so we can design systems that are fault tolerant (google: fault tolerant architectures. lots of good stuff). The costs of the chips will probably direct represent the decrease in yield -- good designs and tools will likely save companies a lot of money (i shouldn't give away my secrets before i patent them
Cooling the higher density chips is probably the most major hurdle towards development of 3-D circuits. A few of these documents hint that microfluidic cooling systems may be the solution. Georgia Tech researchers made an advance on this end a few weeks ago by presenting a microfluidic manufacturing process compatible with standard CMOS design:
http://www.physorg.com/news4657.html
Expect lots of great things in the years to come. For now you can probably expect 3-D integration to creep into specialty mixed signal chips that are extremely expensive, and memory where heat generation is less of a problem. Microfluidic cooling technologies will be adopted in the near term for 2-D high power chips. The first 3-D micro-processor architectures will probably use extra layers for clock distribution, global interconnect systems, and power distribution systems. Caching systems will likely be added to as a third layer until new design approaches (and better tools) allow for the design of multi-layer integration with logic interspersed between the layers.
i've had this idea since I saw my first computer chip back in 1989
You're right--they aren't doing anything new, but your wrong that 3-D integration isn't going to be commonplace very soon.
First off: they don't use Al as the primary interconnect anymore... Cu electrodeposition is the way its been since 130 nm.
Secondly: The chips aren't rough and bumpy due to a process called "Chemical Mechanical Polishing" which essential planarizes the chip. Wafer bonding has been thoroughly studied and chips are already being released that use the process. check out a startup called "ziptronix."
While having more surface area for larger caches or what ever is a wonderful thing, where this stacking concept can really help out is helping with clock sync issues.
Now that we're pushing into the GHz speeds on chips it is getting rather difficult to keep the whole chip in sync across the distances that the signal has to travel. By stacking the various segments of the chip you've eliminated another obstical for higher clockspeeds.
You need to look at the whole picture.
It's not really a case of "where the current is going" - the current flows through the entire circuit, from one side of your voltage source to the other. The important thing to remember is that the current never changes through the whole circuit. The number of electrons/second (amps) is constant through the whole circuit. Only the voltage drop matters as you traverse the circuit. The part of the circuit with the biggest voltage drop across it consumes the most amount of power.
So, you get a small voltage drop across your wires, which gets turned into a small amount of heat. You normally have a large voltage drop across your load, which gets turned into useful work.... plus a bit of heat- nothing's 100% efficient.
For example, in an electric motor, the bulk of it is converted to mechanical work... which is still measured in watts, and *that* eventually gets converted to heat (by friction somewhere). The remainder gets lost due to the resistance in the motor windings.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.
Seymour Cray with the Cray 3 had his processor bricks made of Gallium arsenide. The wikipedia article has flaws (I'll try to fix later) but it has the point that he went down the route of the 3d chip and circuitry much earlier than this /. story.
A brilliant man, Seymour...
Do you know why the road less traveled by is littered with the bones of the unwary?
I'm not sure I understand what you're looking for, but if you simply want the heat as a function of current and resistance, then replace U in equation 2 and you'll get
There you go; you can verify the formula experimentally; double the current and watch the heat output increase four times. It's easiest if you have a calorimeter, but it should be easy to improvise a desktop setup sufficient for a qualitative verification.
PSI is almost upon us.
FYI: PSI is a tale I spun in the '70s or so, when Large Scale Integration (LSI - eventually with a company named after it) and Very Large Scale Integration (VSLI) were industry buzzwords for ICs with a higher level of integration than a single-digit count of gates or flops to be externally interconnected.
PSI would involve:
- constructing a 3-D "chip"
- using ion beam epitaxy and doping to build it up in layers
- testing as you go using electron beams for power and signal injection and higher-voltage electron beams for "positive" voltage injection and as test prods (using secondary emission to pull more electrons than they insert and/or to read the voltage on the chip's internal nodes)
- turning up the beam current to vaporize (and later rebuild correctly) any defective component so the whole thing ends up flawless despite its large gate count. (100% yield!)
- using diamond for the semiconductor (mainly for its stability and heat conduction properties)
- running it in an inert atmosphere (so it can get up to red-hot without burning up or converting into graphite)
- building it as an approximate cube - up to, say, 6 feet on a side
- powering and cooling it on two opposing faces
- with water-cooled silver bus-bars the size of the faces
- connecting it by covering the other four faces with optic fibers for I/O (to interconnect with integrated light-emitting and sensing devices).
Of course the point of the yarn, in addition to potentially being possible, is the appearance of the resulting device:
An enormous supercomputer in the form of a 6-foot cube of diamond, glowing slightly red from operating heat, supported by water-cooled silver bus bars in an inert atmosphere within a glass bottle (ala a vacuum tube), with millions of optic fibers to provide it with sufficient I/O.
Just the sort of thing you'd find as a component in, say, one of the later Skylark spacecraft of E. E. (Doc) Smith's Golden-age SF stories.
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
P = V*(V/R) = V^2R
Shouldn't this be V^2/R?
Resistance contributes quite a bit to heat.
Most examples I have seen here so far have correctly stated Power = Volts * Amps, but incorrectly stated that 'Power' is being dissipated.
Here's an example:
Say you were to place a 4ohm resistor in series with a load, the load would get 1/4 the power it normally gets. In order to provide the load with the proper amount of power, the voltage will need to be increased to bring the watts back to the proper value, thus putting more power into the circuit.
No resistor:
(Power = Volts * Amps) 24Watts = 12VDC * 2ADC
With Resistor:
96Watts = 48VDC * 2ADC
Therefore, more resistance = more heat, WITH A LOAD
I do not see anything about cooling. I mean if the transistor is 3d, this means the warmth is not only created by each part, but some part in the center generate warmth which has to travel toward the outside. Could not this be a big problem ?
C. Sagan : A demon haunted world:
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visit randi.org
"Power" is the measure of energy per time unit ( that is, P = E/t ).
The heat dissipation is directly proportional (by a material-specific constant) with that energy (E), which is
E = P*t = V*I*t = V^2*t/R
As mentioned before, the heat dissipation wont' drop because the resistence is lower, but because that lower resistance allows a similar drop in voltage, and E depends on the square of V
gtkaml.org
Imagine a 1 gb L1 cache layer. In other words, the CPU and RAM are combined in one chip. Then the entire application will be loaded into the CPU/RAM for execution at least 3 times faster.
I would rather Orac on my side.
The Singularity is closer than you think
Quant
don't celebrate just yet,this story can could ver well be tomarrows dupe.... um I meen Reminder.
As if DFM wasn't hard enough for small geometries. This should give EDA vendors an excuse to charge twice and much for their tools.
for years chips have had multi-layered designes. How is this any different?
The wires are not the cause of heat problems. Transistors switching require charging and discharging of capacitors. The formula is approx:
P=1/2cv^2*f
Therefore, lowering the voltage does a lot for power consumuption. However, this usually conincides with an increase in frequency. Since Vcore does not decrease as fast as the frequency is increasing we see net power increase.
This is all dynamic power loss (useful I guess). Since transistors have been shrinking, the leakage currents have been growing exponentially. One of the recent Intel chips leaked about 25A of current as soon as you applied Vcore. That means you were using over 35W of power and got no benefit.
The wires/interconnects are not the major problem for power loss
Wouldn't it make a whole lot more sense just to add a processor on the main memory and let it do all the memory functions?
As I understand it all memory functions are now handled by the Main CPU which does all the orginization and allocation ect..
If a special CPU sat on the memory module then languages like C# and JAVA would see huge speed gains as software memory allocations would be a thing of the past. Just ask the memory to give you SAPCE and it makes room.. OR what may be even better is if the CPU on the MEM module was optimized to handle object references nativly. So that once an object is made in C# then a handle is used then the MEM-CPU could handle that without being told HOW to do so.. less cross talk!!
I know I ant the first to think about this but what do you say? Wouln't this be better than a FASTER CPU, that would end up waiting fir MEM half the time anyway?
Smile.
Now imagine a Beowulf cluster of such chips...
Its amazing what people are motivated to develop when they're confident that they are NEVER getting laid.
(RPI Alums, you know what I mean.)
or maybe the techno-organic one. Or some combination. Human brains aren't binary. Light doesn't need to be binary. We need to start getting places with processors that work on base 10 like we do or even more. What if they worked natively on base 16? Or 7? Or could use variable number bases as best fit the problem?
I think this is where we should be going. I have little faith in the industry to use this advance to cut down heat and waste. I expect we'll be getting the Intel HotCake VI processors out of this more than anything else. Mmmm... a stack of superheated inefficient goodness for your gaming and pr0n vid pleasure...
If my grammar and spelling are off, I am [distracted/tired/careless] (take your pick)
In your frankfurter experiment, The voltage was the same across each of the dogs and so the only thing that was different was the current as a result of the conductivity of the sausages. In this case, P = VI = V^2/R for each of the dogs.
If you had connected the hot dogs in series, like this:You would create a voltage divider network. The analysis for which goes like this: The current through any loop in the circuit is constant (e.g. the same current would be going through both the dogs, but the voltage supply would "see" a higher overall resistance so the total current would be less than in either case.)
In this case, the largest voltage drop is across the higher resistance. since the current is the same through both, the generic dogs will dissipate the most heat in this isntance.
Imagine cutting the generic dog to a length that made it less resistive than the ballpark. In this case, the total current would increase from the previous, and the ballpark would have the large voltage drop.
A simple power supply regulator does just that: it puts a resistance in series with the load and adjusts that resistance so that the voltage across the load is the same no matter the load. This presents some serious efficiency issues when the unregulated voltage is significantly greater than the desired voltage.
In fact, the IC is more complicated than that, introducing parallel and series parallel circuits, and transconductance elements, capacitance and even quantum tunnelling, but suffice to say, in general, the lower the wire resistance, the lower the fraction of heat disipated by the wires themselves.
Can you be Even More Awesome?!
Where C is the capacitance (residual capacitance), V is the voltage and F the switching frequency.
If you don't believe me, check some real research in this area, not your kindergarten texbook, like Wattch
Shorter wires do make C a little bit smaller, but the dominant part there is the gate capacitance.
The Raven
Quick, someone send themselves back in time to blow this guy up.
If you're going back in time, there's no reason to rush. *smirk* They still think time is linear, how quaint.
Anyway I'll keep you guys posted in any case of nanoelectronics advancements. My favorite story would be chips with nanotube wires (or better, transistors). :)
Don't forget to visit physorg frequently, too!
Half-way on topic:
MIT has a team working on a system called Blue Spec, which translates a form of C code into a chip design. It's a multi-stage process - first the C is compiled into Verilog code and translated into an FPGA-based design. The cool part is that their optomizer then cycles through this design and iteratively adds improvements. A design in which they let this cycle run for about 5 days (when printed to silicone) ran only 1.5 times slower than a comparable Intel chip. For a computer-generated design, this is an amazing number.
Wouldn't it be cool to give a program like this an extra dimension to work with? Disregarding "all the things that go wrong," if you built a single core across a few layers, rather than just slapping on a layer of memory and linking it up, I'd imagine that the possibilities for optimizations are greater by orders of mangnitude. Chip designers can only handle so much chip compexity maually, but a computer could just iterate through until it had an optimal design. A program that could do that would take a lot longer to run, but the end product could be pretty cool.
Disclaimer: I learned about the Blue Spec project from one of its engineers, on a bus. I am not affiliated with it in any way, nor can I guarantee personally that any information here is 100% accurate.
I have here in my hand a shiny brand new humor chip upgrade and I want you to use it. This version includes sarcasm detection.
I believe that the "side" residual capacitance given by taller wires doesn't really impact power consumption, it's more of a crosstalk problem.
The Raven
The paragraph after the "code" should read:
You would create a voltage divider network. The analysis for which goes like this: The current through any loop in the circuit is constant (e.g. the same current would be going through both the dogs, but the voltage supply would "see" a higher overall resistance so the total current would be less than in either case.) The current is the same through each of the dogs and the resistance (or at least the relative resistance) is known. The voltage can then be calculated from ohm's law: Vgen = IRgen and Vbpark = IRbpark.
then insert the following after the next paragraph:
The power dissipated is P=VI, in the case of the series connected dogs becomes P=I^2*R, since the current is the same through both dogs, the dog which dissipates the greatest power is the dog with the highest resistance.
Long posts like this are hard to edit, why doesn't slashdot allow limited editing capability?
Can you be Even More Awesome?!
You are one top shelf nerd.
I don't know why (no one know why, maybe it's a slashdot mith) but ENTANGLEMENT CANNOT BE USED FOR COMMUNICATING DATA!
Yeah. Would you choose a neurosurgeon who pokes around people's brains in his spare time? I wouldn't.
Data points. 3D devices have been created already, as we have done it. Processors and memory, FPGAs, CMOS sensors... And these are truely 3D. They started life as seperate 8" wafers. The interconnect is through the wafer and we can have as many as 450K per sqmm. Each additional layer adds ~12um. The problem with heat is no worse in 3D ICs than in 2D - it also no better. You do get a power benefit from 3D. It can be very significant. All power, except leakage is the result of the switching capacitance of the circuits. About half of the capacitance is in the wiring at 130nm. With each generation the wire capacitance is increasing and this is creating a fundemental speed limit in ICs. ( wires get smaller increasing R and closer together incresing C) Pads today can be placed anywhere on the die and often are. The chips are then Flip-chipped to a substrate (package) This is typical in most Intel, AMD, IBM, etc processors. Yield and Cost Yield is per sqmm, no matter 2D or 3D. If a 100sqmm IC yields %50 in 2D, cutting it into 4 25sqmm chips and stacking them still gives %50 yield. You would however reduce the power or increase the performance depending on the tradeoffs exercised. The cost of stacking wafers is about the same as adding another layer of metal to a wafer The surface on most wafers below the ~180nm processing node are planarized. Thus the surfaces are typically flat to ~+/-1um across an 8" wafer. Interconnect below 180nm is almost all copper. This provides lower resistance and works better with the methods to give planar surfaces. In reality, the process for wire is to first put down glass. Then trench into the glass a channel, deposit a barrier to keep the copper from moving around, then deposit copper seed crystals, then lastly plate the copper on to the surface. After this the copper is polished down to the glass surface. DRAMs and Flash still tend to use only aluminum metal systems even at 90nm. DRAM often uses 2 polysilicon layers. Flash and EEPROM also. But virtually all other ICs only have a single poly layer. The resistance is ~100x greater than metal. Regards,
You are right, but wires are the primary source of the capacitance.
FYI the leakage is the result of the very thin glass between the gate and the substrate. (@90nm gate oxide is about 15 angstroms) This leakage is the same as the tunneling which is done to program flash or EEPROM. Of course, in flash or EEPROM you only provide the programming voltage for milliseconds, not forever.