All FPGA's have cross-point which are connected are left open based on a bit stream. This bit stream is usually present in a EEPROM/EPROM which you program and on startup this program the FPGA. This has been out there in most networking (ever done a firmware upgrade) and other backplane processors. One important reason this is not sued in main stream processors are the time to boot-up and program the cross-points. Also Processors these days tend to run at ASIC timing optimized speeds which an FPGA can never support (mainly because of the increased wireload delay caused by long cross-point wires). One other good reason is processors these days tend to heat up a lot (about 100C) and there is no reliable high-temperature EEPROM that would have reliable long life at this temperature. I am really not sure if this guy has been able to address atleast one if not all of these challenges.
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All FPGA's have cross-point which are connected are left open based on a bit stream. This bit stream is usually present in a EEPROM/EPROM which you program and on startup this program the FPGA. This has been out there in most networking (ever done a firmware upgrade) and other backplane processors. One important reason this is not sued in main stream processors are the time to boot-up and program the cross-points. Also Processors these days tend to run at ASIC timing optimized speeds which an FPGA can never support (mainly because of the increased wireload delay caused by long cross-point wires). One other good reason is processors these days tend to heat up a lot (about 100C) and there is no reliable high-temperature EEPROM that would have reliable long life at this temperature. I am really not sure if this guy has been able to address atleast one if not all of these challenges.