Arrays of FPGAs w/o an operating system fall into a class of either embedded or external "computing accelerators". Having developed applications on a number of these kinds of devices (Pixar Image computer, AT&T pixel machine, IBM PVS, custom built 2048 processor systems and embedded FPGA board-level products), the main problem is I/O. Once data has been loaded, things are great. The rub is loading and unloading the data and/or streaming at DMA rates (in & out simultaneously) all tend to leave the "computing accelerator" significantly underutilized. A lot of attention (and expense) has to be put into the I/O subsystem s to make something truly useful.
Slashdot Mirror
Arrays of FPGAs w/o an operating system fall into a class of either embedded or external "computing accelerators". Having developed applications on a number of these kinds of devices (Pixar Image computer, AT&T pixel machine, IBM PVS, custom built 2048 processor systems and embedded FPGA board-level products), the main problem is I/O. Once data has been loaded, things are great. The rub is loading and unloading the data and/or streaming at DMA rates (in & out simultaneously) all tend to leave the "computing accelerator" significantly underutilized. A lot of attention (and expense) has to be put into the I/O subsystem s to make something truly useful.