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Analyzing the RISC-V Instruction Set Architecture â" Andreas Olofsson, August 2014

The RISC-V architecture is not revolutionary, but it is an excellent general purpose architecture with solid design decisions. The true breakthrough here is really the open source licensing model and the maturity of the design as compared to most other open source hardware projects. ... A royalty free 64-bit RISC-V core would have a raw silicon cost of a couple of cents in current CMOS process nodes. Now that is exciting!

http://www.adapteva.com/epipha...
64 cores, mesh network that extends off the chip, in production.</p><p>Try harder MIT :-p</p></quote>

They already tried harder : http://www.tilera.com/. And as another post mentioned, Intel Knights Corner is cache coherent on 61 cores (62 architectured).

The summary doesn't get the point of the article: what's novel is not the presence of cache coherency, it's just the new way of implementing snoop-based cache coherency over their network. Cache coherency for a large number of cores can be very expensive time-wise, so any idea to improve it is more than wecome.

http://www.adapteva.com/epipha...
64 cores, mesh network that extends off the chip, in production.

Try harder MIT :-p

simply put, this is a very expensive way to do things. the Kinect has done a good job at motion capture so why not just improve on that idea? using multiple (cheap-o) cameras at different angles, you could not only capture one person but multiple people without putting on any annoying suits or even extend the area of capture. what's better is that it scales as you can add more and more cameras and create a more accurate model which means it would solve occlusion issues. just to sweeten the deal, you could use optical flow to predict future motion and thus remove any possible lag you may encounter. this would be a great use case for Epiphany III manycore processor as it could process every camera at the same time.

the bottom line is that while this military-grade motion sensing stuff may be a great but it's going to be expensive ($350 per unit from what i see on KS) and there are going to be a LOT of hardware support issues.

Further reading:
3D Reconstruction from Multiple Images
Optical Flow

The ISA is in appendix A: http://www.adapteva.com/support/docs/e3-reference-manual/

you need to fill the SIMD units to get theoretical performance on a i7 (or similar). with epiphany it may be easier to get close to the theoretical FLOPS
http://www.adapteva.com/white-papers/ten-myths-debunked-by-the-epiphany-iv-64-core-accelerator-chip/

Also you save lots of power, because you dont have vast amounts of cache (though this may effect performance for some cases), and the architecture is much simpler, with only the instructions needed (not decades of x86 legacy). last time i was in an HPC machine room, there was a pile of not very old xeon servers in the corner, still fast machines, but not worth the energy cost to run them compared to the new servers.

your wish on the clusters has been answered. http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/posts/323994

i agree that the 64core versions is far more exciting than the 16core version. i guess maybe they think there is a lot higher risk there (they have already made and tested a small number of 16core chips, http://www.adapteva.com/wp-content/uploads/2011/06/adapteva_mpr.pdf )

>As for apples to apples, It's vaporware specs read similar to the old printout of the vaporware specs for the Propeller2 from microchip inc on my desk.

they have working 16 core silicon. they shared the cost of a 65nm wafer with other companies small run asics. this lowers the entry cost to making silicon, but gives a crazy high per unit cost. if they raise enough money to do a full wafer at 28nm, then it becomes cost effective. there are intersting details and numbers on page 3 of http://www.adapteva.com/wp-content/uploads/2011/06/adapteva_mpr.pdf

Good god, I had to actually load a PDF to find out the answer. You use C in Eclipse and GDB for debugging.