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If you want a MIPS implementation that you can run in an FPGA, then we've built one and released it under an Apache-style license (not exactly the Apache license, because the Apache license says 'the software' in a lot of places). It's an implementation of a version of the (64-bit) MIPS ISA that is over 20 years old, so any relevant patents have expired. We've been using this in teaching for a couple of years (one exercise is to replace the branch predictor, for example). It's written in a high-level HDL, so more amenable to research and teaching uses, because the code is easy to make invasive changes to.

It's not clear what version of the MIPS ISA they're implementing (the article I read just said MIPS32, which covers a whole range of things). It sounds like it's MIPS32r6, which is not backwards compatible with any previous MIPS version. The only value of MIPS over something like RISC V (which is increasingly the standard ISA for computer architecture research) is that there's a large body of existing software for it, so you can do real evaluation.

We've done a clean-room reimplementation of MIPS III (R4K compatible) implementation in BlueSpec, which is a high-level HDL. MIPS III and the R4K are over 20 years old, so any architecture-specific patents will have expired. In comparison, this core is only 32-bit (really not interesting for research) and is written in a low-level HDL (making the kind of invasive changes that you want to do in research difficult), and is an ISA that has very little software support.

Any suggestions on that FPGA board?

We use the Terasic DE4 for most things, but it's insanely expensive - definitely only a board to use if someone else is paying. The SoCKit is quite nice - much cheaper and has a dual-core ARM board. We've ported FreeBSD to the ARM (adding devices for programming the FPGA) and our MIPS-compatible softcore to the FPGA, with virtio communicating between the two, which makes it easy to play with heterogeneous multicore. It's mainly intended for prototyping accelerator cores and there's a fast cache-coherent interconnect between the ARM cores and the FPGA so it's quite a nice platform to play with if you want to try and offload computation to the FPGA. It's a fairly small FPGA by modern standards, but still big enough for our CPU, which is a 6-stage in-order pipeline with caches, TLB, branch predictor and so on.

There's no price yet because they're giving away the first production run to people who are going to do interesting things with them. Unfortunately, this is a really bad time to do anything MIPS related (and I say this as someone who hacks on a MIPS IV compatible softcore and the LLVM MIPS back end). Imagination has just released the MIPS64r6 and MIPS32r6 specs. These are the biggest revisions to the MIPS ISA since MIPS III, which introduced 64-bit support. They've removed a load of legacy crap like the lwr and lwl instructions and the branch-likely instruction family and added things like compact (no delay slot) branch instructions, the requirement that hardware supports unaligned loads and stores (or, at least, that the OS traps and emulates them), and added much better support for PC-relative addressing. The result is a nice ISA, which is not backwards compatible with MIPS32r2 or MIPS64r2, the ISA that these boards use. Any investment in software for MIPS now is going to be wasted when products with the new ISA come out.

It is possible, but for good performance it needs hardware support. We've implemented hardware-enforced bounds checking for C code using our processor. If you only care about accidental bugs and not about a malicious attacker, and don't use threads (or are happy to bound every pointer store with a transactional region), and don't mind that the semantics of C are subtly broken in the kinds of permitted pointer operations, then Intel's Memory Protection Extensions will do the same thing.

The reason that we've open sourced our CPU (not the one in TFA) is to promote research. The vast number of papers published in computer architecture conferences and journals evaluate their approach solely on a simulator and hope that there's some relationship between the simulator and reality. While a softcore CPU is not exactly like a real CPU, being able to implement your ideas in an FPGA (and pass timing!) does at least mean that it is possible to implement them in a real CPU, although it doesn't guarantee that they'd be more efficient than another approach. It also lets you do evaluation with real software: we can boot FreeBSD on our system and run real programs on it for benchmarking, which is a lot more realistic than taking some existing instruction trace, permuting it based on some assumptions, and then feeding it into your simulator.