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overheardinpdx quotes HPCwire: Wednesday a company called Bounded Floating Point announced a "breakthrough patent in processor design, which allows representation of real numbers accurate to the last digit for the first time in computer history. This bounded floating point system is a game changer for the computing industry, particularly for computationally intensive functions such as weather prediction, GPS, and autonomous vehicles," said the inventor, Alan Jorgensen, PhD. "By using this system, it is possible to guarantee that the display of floating point values is accurate to plus or minus one in the last digit..."

The innovative bounded floating point system computes two limits (or bounds) that contain the represented real number. These bounds are carried through successive calculations. When the calculated result is no longer sufficiently accurate the result is so marked, as are all further calculations made using that value. It is fail-safe and performs in real time.
Jorgensen is described as a cyber bounty hunter and part time instructor at the University of Nevada, Las Vegas teaching computer science to non-computer science students. In November he received US Patent number 9,817,662 -- "Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof." But in a followup, HPCwire reports: After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, The End of Error, which was published 19 months before Jorgensen's patent application was filed. We regret the omission of this information from the original article.

An anonymous reader writes "A mystery [Major League Baseball] team has made a sizable investment in Cray's latest effort at bringing graph analytics at extreme scale to bat. Nicole Hemsoth writes that what the team is looking for is a "hypothesis machine" that will allow them to integrate multiple, deep data wells and pose several questions against the same data. They are looking for platforms that allow users to look at facets of a given dataset, adding new cuts to see how certain conditions affect the reflection of a hypothesized reality."

An anonymous reader writes "As Nicole Hemsoth over at HPCwire reports 'In a nutshell, the Automata processor is a programmable silicon device that lends itself to handing high speed search and analysis across massive, complex, unstructured data. As an alternate processing engine for targeted areas, it taps into the inner parallelism inherent to memory to provide a robust and absolutely remarkable, if early benchmarks are to be believed, option for certain types of processing.'" Basically, the chip is designed solely to process Nondeterministic Finite Automata and can explore all valid paths of an NFA in parallel, hiding the whole O(n^2) complexity thing. Micron has a stash of technical documents including a paper covering the design and development of the chip. Imagine how fast you can process regexes now.

An anonymous reader writes "With help from a draft report (PDF) from Oak Ridge National Laboratory's Jack Dongarra, who also spearheads the process of verifying the top of the pack supercomputer, we get a detailed look at China's Tianhe-2 system. As noted previously, the system will be housed at the National Supercomputer Center in Guangzhou and has been aimed at providing an open platform for research and education and to provide a high performance computing service for southern China. From Jack's details: '... was sent results showing a run of HPL benchmark using 14,336 nodes, that run was made using 50 GB of the memory of each node and achieved 30.65 petaflops out of a theoretical peak of 49.19 petaflops, or an efficiency of 62.3% of theoretical peak performance taking a little over 5 hours to complete.The fastest result shown was using 90% of the machine. They are expecting to make improvements and increase the number of nodes used in the test.'"

Nerval's Lobster writes "T-Platforms, which manufactured the fastest supercomputer in Russia (and twenty-sixth fastest in the world), has been placed on the IT equivalent of the no-fly list. In March, the U.S. Department of Commerce's Bureau of Industry and Security added T-Platforms' businesses in Germany, Russia and Taiwan to the 'Entity List,' which includes those believed to be acting contrary to the national security or foreign policy interests of the United States. U.S. IT companies are essentially banned from doing business with T-Platforms, especially with regards to HPC hardware such as microprocessors, which could be used for what the government views as illegal purposes. The rule, discovered by HPCWire, was published in March. According to the rule, Commerce's End-User Review Committee (ERC) believes that T-Platforms may be assisting the Russian government and military conduct nuclear research — which, given historical tensions between the two countries, apparently falls outside the bounds of permitted use. An email address that T-Platforms listed for its German office bounced, and Slashdot was unable to reach executives at its Russian headquarters for comment."

MrSeb writes with an article in Extreme Tech about the Titan supercomputer. From the article: "Cray, AMD, Nvidia, and the Department of Energy have announced that the Oak Ridge National Laboratory's Jaguar supercomputer will soon be upgraded to yet again become the fastest HPC installation in the world. The new, mighty-morphing computer will feature thousands of Cray XK6 blades, each one accommodating up to four 16-core AMD Opteron 6200 (Interlagos) chips and four Nvidia Tesla 20-series GCGPU coprocessors. The Jaguar name will be suitably inflated, too: the new behemoth will be called Titan. The exact specs of Titan haven't been revealed, but the Jaguar supercomputer currently sports 200 cabinets of Cray XT5 blades — and each cabinet, in theory, can be upgraded to hold 24 XK6 blades. That's a total of 4,800 servers, or 38,400 processors in total; 19,200 Opterons 6200s, and 19,200 Tesla GPUs. ... that's 307,200 CPU cores — and with 512 shaders in each Tesla chip that's 9,830,400 compute units. In other words, Titan should be capable of massive parallelism of more than one million concurrent operations. When the server is complete, towards the end of 2012, Titan will be capable of between 10 and 20 petaflops, and should recapture the crown of Fastest Supercomputer in the World from the Japanese 'K' computer."

gupg writes "When China built the world's fastest supercomputer based on NVIDIA GPUs last year, a lot of naysayers said this was just a stunt machine. Well, guess what — here comes the science! They are working on better material for solar panels and they ran the world's fastest simulation ever. NVIDIA (whose GPUs accelerate these applications as a co-processor) blogged on this a while ago, where they talk about how the US really needs to up its investment in high performance computing."

An anonymous reader writes "Supercomputer giant Cray has lifted the lid on its first GPU offering, bringing it into the realm of top supers like the Chinese Tianhe-1A" The machine consists of racks of blades, each with eight GPU and CPU pairs (that can even be installed into older machines). It looks like Cray delayed the release of hardware using GPUs to work on a higher level programming environment than is available from other vendors.

rubycodez writes "The Tianhe-1A system will be the last Chinese supercomputer to use imported Intel and AMD processors. By years end, China's own 64 bit MIPS-compatible 65nm 8-core 1GHz version of the Godsen (Longsoon family) processors will be used, including 10,000 of them for the 'Dawning 6000' supercomputer. Yes, the chips can and usually do run GNU/Linux, but also can run FreeBSD, OpenBSD, and NetBSD."

An anonymous reader writes "Microsoft has unveiled the largest and clearest image of the night sky ever assembled. This so-called 'TeraPixel' sky map was generated with the help of some of Microsoft's latest HPC and parallel software assets. Quoting: 'Compared to the old sky image, the TeraPixel version is much more refined. With all the artifacts, seams and inconsistencies processed away, it looks like a true unified image of the sky above. It's like going from Super Mario Brothers on 1985-era Nintendo consoles to Halo 2 on Xbox 360s.'" You can view the image at Microsoft's WorldWide Telescope site — it requires the Silverlight plugin for Windows or Mac. No word at the site about Linux or whether Moonlight works there.

blair1q writes "Using a four-tiered architecture (from CERN's central computer at Tier 0 to individual scientists' desk/lap/palmtops at Tier 3), CERN is distributing LHC data and computations across resources worldwide to achieve aggregate computational power unprecedented in high-energy physics research. As an example, 'researchers can sit at their laptops, write small programs or macros, submit the programs through the AliEn system, find the necessary ALICE data on AliEn servers, then run their jobs' on upper-tier systems. The full grid comprises small computers, supercomputers, computer clusters, and mass-storage data centers. This system allows 1,000 researchers at 130 organizations in 34 countries to crunch the data, which are disgorged at a rate of 1.25 GB per second from the LHC's detectors."

anzha writes "It seems that that Linux Networx, the pioneering Linux supercomputing company, has gone belly up. SGI announced that it has bought the core assets of LNXI. Furthermore, the rumors are that the doors were locked and employees were just given their paychecks. This analysis, on the other hand, claims that SGI has 'made employment offers to many LNXI engineers.' It's unclear what kind of support will be extended to customers of LNXI's Clusterworx Advanced products. What does this mean for the future of Linux supercomputing?"

meanonymous writes "HPCWire reports that a unique marketing model for 'manycore' processors is being proposed by University of Illinois at Urbana-Champaign researchers. The current economic model has customers purchasing systems containing processors that meet the average or worst-case computation needs of their applications. The researchers contend that the increasing number of cores complicates the matching of performance needs and applications and makes the cost of buying idle computing power increasingly prohibitive. They speculate that the customer will typically require fewer cores than are physically on the chip, but may want to use more of them in certain instances. They suggest that chips be developed in a manner that allows users to pay only for the computing power they need rather than the peak computing power that is physically present. By incorporating small pieces of logic into the processor, the vendor can enable and disable individual cores, and they offer five models that allow dynamic adjustment of the chip's available processing power."

slashthedot sends us to High Productivity Computing Wire for a look at the effort to beef up computing and communications infrastructure at a number of US universities in preparation for the data deluge anticipated later this year from two experiments coming online at CERN. The collider will smash protons together hoping to catch a glimpse of the subatomic particles that are thought to have last been seen at the Big Bang. From the article: "The world's largest science experiment, a physics experiment designed to determine the nature of matter, will produce a mountain of data. And because the world's physicists cannot move to the mountain, an army of computer research scientists is preparing to move the mountain to the physicists... The CERN collider will begin producing data in November, and from the trillions of collisions of protons it will generate 15 petabytes of data per year... [This] would be the equivalent of all of the information in all of the university libraries in the United States seven times over. It would be the equivalent of 22 Internets, or more than 1,000 Libraries of Congress. And there is no search function."

Emulex's LightPulse family of 4 Gb/s HBAs is showing great results with AMD Opteron processor-based systems. "Emulex 4 Gb/s HBAs running in conjunction with AMD Opteron processors provide as much as a 78 percent performance advantage across a range of I/O workload requests when compared with competitive offerings." Emulex and AMD have worked closely together to promote interoperability, and to ensure customer have access to performance-driven solutions. "In addition, Emulex is working with AMD to develop solutions around next-generation products, such as those optimized for server virtualization environments." "The high-performance combination of Emulex's flexible and reliable 4 Gb/s HBAs with the AMD Opteron processor delivers unique and compelling benefits to our customers who require high levels of performance," said Mike Smith, executive vice president of worldwide marketing, Emulex. "Working with AMD to deliver industry-leading, high-performance solutions also ensures support for next-generation technology innovation, such as server virtualization."

prostoalex writes "High Performance Computing Newswire is running an article on a paper by computer scientists at the U.S. Department of Energy's Lawrence Berkeley National Laboratory. They have evaluated the processor's performance in running several scientific application kernels, then compared this performance against other processor architectures. The full paper is available from Computer Science department at Berkeley."

David Greene writes "HPCWire has a story about Cray's newly-introduced vision of Adaptive Supercomputing. The new system will combine multiple processor architectures to broaden applicability of HPC systems and reduce the complexity of HPC application development. Cray CTO Steve Scott says, 'The Cray motto is: adapt the system to the application - not the application to the system.'"