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Asynchronous CPUs exist by riedquat · 2001-03-04 21:12 · Score: 1 · on Clockless Computing?

Asynchronous CPUs exist. Have a look here. It's a commercial 32-bit system-on-chip with an Amulet asynchronous core. Even that article's a year old.

Re:P4 & RAMBUS (The Clown) by Meenky · 2000-08-20 21:54 · Score: 1 · on Intel Pentium 4 NetBurst Architecture Explained

Found it!!!

I just found the URLs I wanted. These people make QDR memory and these people make the controller. Now this is SRAM memory, not DRAM, but I don't think it would be too hard to make a mobo that took this, couldn't be anymore expensive than RAMBUS could it? Plus the controller has a sustained thoughput of 7.2GBps at 100MHz, WOW!!!!!

The world really is round and aliens are not stealling your socks...

"Kicking out the Clock" by Amulet's lead, Furber by BitMan · 2000-05-15 00:52 · Score: 4 · on Self-Timed ARM Provides Low Power Consumption

Amulet's lead, Steve Furber (who also designed the original ARM), wrote a recent editorial coverstory called "Kicking out the Clock" in the May 2000 edition of Integrated System Design (ISD) magazine.

In the article, he used an example of a "dual-rail" logic (as opposed to "single-rail" found in most boolean-designs) call Null Convention Logic (NCL) from Theseus Logic. Theseus' NCL approach not only goes a long way to not only solving the power and noise problems (like most asynchronous), but also the greater problem of design reuse (a problem with both async and, especially, synchronous) -- the later is something Furber was quoted on in a past EE Times article (cannot seem to find it on-line anymore?).

Timing verification is becoming increasingly difficult in IC design, adding rediculous ammounts of extra effort and, in some cases, complete design failures (e.g., AMD, IBM and Intel have all had timing-related design failures). Clocks may soon disappear in favor of async designs, especially those like Theseus Logic's nearly-100% delay INsensitive NCL technology. NCL's delay INsensitive nature comes from the fact that it is NOT boolean logic based, but a new method that breaks the traditional foundation of what boolean logic was design for, mathematicians, not computers.

In addition to an "operand" and an "operator," as with traditional, human-based math, computers require a third "control" line. In synch/boolean, this is the clock. With the limitations of the speed of light, it is IMPOSSIBLE for 10M+ transistor ICs on one section of the chip to be timed synchronous with another. As such, most modern ICs have localized clocks, which further adds to design complexity.

NCL removes the clock as the control (as with most async) *BUT* it places the control back in the data flow lines themselves! NCL is a 3-state logic of "true" and "false", plus the control which is derived from NCL math to be "null" (no data). This representation is 2NCL in NCL math (see Theseus' site for more details on NCL including 4NCL and 3NCL, the later being used with most off-the-shelf tools and optimizers). In 2NCL, the lines (again, "dual-rail") puts the false value (0) on one line and true (1) on the other line *IF* voltage is present, otherwise, no voltage (or low) results in the state of "null" (again, no data). Acknoledgements are used to maintain a delay INsensitive combinational logic circuit, including the fact that NCL can be place alonside synch/boolean and maintain 100% data flow and integrity (again, totally delay INsensitive). So instead of data having to "wait" on a clock to move forward, data moves forward when it arrives! This further increases performance!

Although Theseus' NCL technology is NOT boolean based, it works with off-the-shelf synch/boolean IC design tools (unlike attempts like Cogency's), it is still CMOS-based, and it not too difficult for an engineer to learn coming from the synch/boolean world.

[Bias: I am an employee of Theseus Logic and know Mr. Furber, the Amulet lead. I am NOT an engineering lead, just a regular engineer (who seconds as the sysadmin ;-).]

-- Bryan "TheBS" Smith

"Kicking out the Clock" by Amulet's lead, Furber by BitMan · 2000-05-15 00:52 · Score: 4 · on Self-Timed ARM Provides Low Power Consumption

Amulet's lead, Steve Furber (who also designed the original ARM), wrote a recent editorial coverstory called "Kicking out the Clock" in the May 2000 edition of Integrated System Design (ISD) magazine.

In the article, he used an example of a "dual-rail" logic (as opposed to "single-rail" found in most boolean-designs) call Null Convention Logic (NCL) from Theseus Logic. Theseus' NCL approach not only goes a long way to not only solving the power and noise problems (like most asynchronous), but also the greater problem of design reuse (a problem with both async and, especially, synchronous) -- the later is something Furber was quoted on in a past EE Times article (cannot seem to find it on-line anymore?).

Timing verification is becoming increasingly difficult in IC design, adding rediculous ammounts of extra effort and, in some cases, complete design failures (e.g., AMD, IBM and Intel have all had timing-related design failures). Clocks may soon disappear in favor of async designs, especially those like Theseus Logic's nearly-100% delay INsensitive NCL technology. NCL's delay INsensitive nature comes from the fact that it is NOT boolean logic based, but a new method that breaks the traditional foundation of what boolean logic was design for, mathematicians, not computers.

In addition to an "operand" and an "operator," as with traditional, human-based math, computers require a third "control" line. In synch/boolean, this is the clock. With the limitations of the speed of light, it is IMPOSSIBLE for 10M+ transistor ICs on one section of the chip to be timed synchronous with another. As such, most modern ICs have localized clocks, which further adds to design complexity.

NCL removes the clock as the control (as with most async) *BUT* it places the control back in the data flow lines themselves! NCL is a 3-state logic of "true" and "false", plus the control which is derived from NCL math to be "null" (no data). This representation is 2NCL in NCL math (see Theseus' site for more details on NCL including 4NCL and 3NCL, the later being used with most off-the-shelf tools and optimizers). In 2NCL, the lines (again, "dual-rail") puts the false value (0) on one line and true (1) on the other line *IF* voltage is present, otherwise, no voltage (or low) results in the state of "null" (again, no data). Acknoledgements are used to maintain a delay INsensitive combinational logic circuit, including the fact that NCL can be place alonside synch/boolean and maintain 100% data flow and integrity (again, totally delay INsensitive). So instead of data having to "wait" on a clock to move forward, data moves forward when it arrives! This further increases performance!

Although Theseus' NCL technology is NOT boolean based, it works with off-the-shelf synch/boolean IC design tools (unlike attempts like Cogency's), it is still CMOS-based, and it not too difficult for an engineer to learn coming from the synch/boolean world.

[Bias: I am an employee of Theseus Logic and know Mr. Furber, the Amulet lead. I am NOT an engineering lead, just a regular engineer (who seconds as the sysadmin ;-).]

-- Bryan "TheBS" Smith

About EMI by Wreck · 2000-04-26 21:17 · Score: 2 · on Create Your Own Psuedo-RDRAM

I was curious as to whether there was really a need for an EMI shield on memory. Clearly, the author of the article thought it mattered (though it was funny that he could not get his system to 150Mhz anyway... so what was the point of it all?)

Anyway, I went to google for some links.

Here is a fairly general overview of EMI in computers. It talks about various strategies for dealing with it.

Here is an article mostly about SDRAM, but which says the following: "Spread Spectrum Clocking (SSC) is a frequency modulation technique for EMI reduction. In the latest motherboards, the master clock generator chip does not maintain a constant frequency." Anyone know if that is true? I didn't know that...

Finally, an article showing Intel is concerned about the problems of EMI in modern computers.

All in all, interesting stuff (I love absurb overclocking articles!) but I would like to have found some evidence that shielding memory like they did has any real benefit.

Re:This contest lacks proof....... by dhart · 1999-10-29 08:10 · Score: 1 · on Worlds Slowest NT Server

Nice Script. However, I doubt that using a batch file is a Microsoft approved method.

Microsoft spokesperson Dan Small once said "Yeah, but the scripting is almost a failing of Unix, not a virtue".