Slashdot Mirror
Intel Pentium 4 NetBurst Architecture Explained
fr0child writes "Next week is Intel's Developer Forum (IDF) and it seems they'll be releasing quite a bit of information (aka hype) about the Pentium 4. Anandtech seems to have gotten the scoop on Intel's NetBurst Architecture, basically covering the P4's internal architecture."
P.S. You can also get the scoop over at sharky extreme.
Simply asked, if NVIDIA is cramming so much in their GPU, which is about to be challenged by Intel P4, would they be able to react by bringing out a central processing unit ?
I'm still trying to figure out what people mean by 'social skills' here.
Using RAMBUS-only also cuts out the smart market :-)
# debian/rules
I was always under the impression that RISC meant reduced instruction set computing and cisc complex instruction set computing..
Ask and you shall receive.(Not that I claim to be a genius about these things ;)
CPU pipelining in general is a divide-and-conquer scheme. Say you have some set of tasks, each of which you know you can do in ten minutes (take out trash, vaccuum living room, rebuild the linux kernel, etc.) What if you could break each of these down into smaller steps (like finding the trash, collecting it, taking the bag to the curb). Say each of these smaller steps takes no more than three minutes.
Now, you've got a lot of the large-scale tasks to do, so you invite a bunch of your friends over. Each person takes a specific task and does it in assembly line fashion.
Here's the scenario:
Oops! we're at 12 minutes, that's 2 minutes more than it takes me to do it by myself. But wait, how long does it take to get the next bag to the curb? If the searcher started looking for more trash as soon as he gives the first trash to the collector, he now has more trash ready to be colleted. Follow this through, and you get something that looks like this (apologies for the strangely aligned ascii-art):
-----------------------------------------
|_search__|_collect_|___bag___|___dump__|
-----------------------------------------
|_block1__|__NOP____|___NOP___|___NOP___|
|_block2__|__block1_|___NOP___|___NOP___|
|_block3__|__block2_|__block1_|___NOP___|
|_block4__|__block3_|__block2_|__block1_|
|_block5__|__block4_|__block3_|__block2_|
(and so on)
As you can see, by the time the dumper gets around to dumping block1, we have block2 (the next bag of trash) ready for him to dump. If everything proceeds in "lock-step" (that is, no one gets ahead of the others), then after that first bag of trash, we can dump a bag every 3 minutes. This is much faster than on bag every 10 minutes, and this is the most common type of speedup associated with piplining.
The first part (where various people are standing idle is called "filling the pipe." Certain pieces stand empty because we're working on the first instruction, and we just haven't gotten to them yet. In a CPU for example, the ALU will usually stand idle until the instruction decode logic has examined the bit arrangement of the instruction word and determined whether we should be ADDing, MOVing, BRAnching, or whatever.
Oh, and that brings up branches. Say you've got to stop bagging trash and start washing dishes or something. Everyone has to stop what they're doing (once they're finished with the tasks still waiting on them), and start work on something else. Sometimes we know this is coming and have prepared for it (known as "branch prediction"), but sometimes we guess wrong (say we thought we'd be doing laundry next). Now we not only are switching jobs, but we're switching to something unexpected. This can essentially cause us to skip a beat. This means that for a moment or two, someone (or two, or everyone) will have nothing to do. Then the pipe fills again and we're back up to speed.
CPU designers spend lots of time trying to find new ways to keep the pipe full, because, as you can see, the more a pipe stays full, the faster a system is overall. This is why branch prediction is so important. In addition to branch prediction, there's a whole slew of techniques, like "out of order execution," that allow us to make up time in other ways.
This is a four-stage pipeline. Imagine what's going on with Intel's 20-stage monster! If we can continually decrease the amount of time taken by the longest stage in the pipline, then we can generate more instructions per second: we still have 1 instruction per clock (IPC), but if we can speed up the clock, we get more throughput (IPS). How can we speed up the clock? We do less in each clock cycle and spread the instruction out over more pipeline stages.
This is a really simple overview. There's lots more where this came from, and it's all really neat stuff for those interested in hardware. For those interested, I'd recommend a book or course in hardware organization. You'll need a working knowledge of logic gates, some combinatorics, and some circuit design skills, but it's worth it!
--
yeah, OC Workbench has a little thing with a link to some high-magnification pictures of what can happen to your CPU if you don't treat it OK. Can you say "sliced Pentium"?
Members of the Society for the Prevention of Cruelty to CPUs (SPCC) should not look....! It looks like it could have hurt ("megahurt", as The Register has it).
Liquid cooling indeed. Why do I feel we have come full circle? I remember the liquid cooled machines at CERN - I thought we had gotten rid of those....
Hi!
I am tired of seeing Intel put out more and more vaporware. RDRAM, IA-64, etc, etc..
You can buy RDRAM right now if you want to. Hardly vapour.
Engineering prototypes of the IA-64 have been around for a while, with every indication that they will ship. Doesn't look very vaprous to me.
IA-64 has 1/5 the performance of an alpha under gcc, which is not optimised for the alpha. (likely the kind that is 3x an Athlon or more for a P3)
Firstly, GCC is not the best compiler in the world. When comparing an Alpha to an IA-64 chip, I'd use Intel's compiler on the IA-64 and Compaq's compiler on the Alpha. Both companies have a history of writing compilers that were extremely well optimized for their platforms.
Secondly, I don't see much support for your figures. See my next point.
Even a 2 year old alpha can beat most P3s (1.5 -2x P3 MHz = alpha MHz in performance)
Not really. Alpha chips are about even in everything except floating point (where the Alpha blows *everyone* out of the water - Sun, HP, IBM, Motorola, etc).
They do this with the higher speed grades of their chips that were released _recently_. Older chips used the same design but were clocked more slowly, and don't blow away present chips.
Check http://www.spec.org for reasonably accurate benchmark information. They use the fairest system for evaluation that I've seen (standard test code supplied by SPEC, compilation and system tweaking handled by the companies owning the platforms being tested).
As far as the performance of the Alpha or an Athlon vs. the P4 goes... The P4 is still in the final debugging stages. Wait six months and look for SPEC marks.
Personally, I'd like to see SPEC marks for the G4. Apple has been allergic to SPEC of late.
The author of that quote was clueless and should have said "microarchitecture". The architecture of Pentium 4 is very similar to Pentium III, but the microarchitecture is 100% different, and is a complete overhaul.
1) Pipeline stalls / operand latency:
If the compiler and/or CPU is unable to reorder instructions effectively (or if a particular piece of code is not amenable to reordering), then an instruction in the pipeline may not have it's operands ready when it needs them and will stall the pipeline waiting for them. With a longer pipeline it will take more clock ticks for the necessarty operands to work their way thru the pipeline to clear the stall. Intel have added a double clock speed arithmetic unit (ALU) to the P4 to try to mitigate operand latency.
2) Branch mispredict penalty:
When a modern CPU such as the P4 encounters a branch instruction, it predicts whether the branch will be taken or not (by using the execution history) in order to be able to continue processing instructions through the pipeline. When the branch is finally evaluated near the end of the pipeline it may turn out that the prediction was wrong, and that all the instructions following the branch (now in the pipeline) should not ne executed. In this case the processor has to flush the pipeline and instead take the correct branch. This "pipeline flush" branch mispredict penalty is obviously higher the longer the pipeline is - a 20 stage pipeline means you are throwing away 20 instructions when a branch is mispredicted.
P4 was designed with a long pipeline so that each pipeline step could be very simple/quick and therefore the processor could have a very high clock rate. The downside of doing this is the above two problems, which mean that the average number of instructions executed per clock cycle (IPC - aka processor efficiency) gets reduced.
P4 at 1.4GHz may be faster than P3 at 1GHz, but because P4 will have a lower IPC than P3, it won't be as fast as a 1.4GHz P3 (if we ever see one) or 1.4GHz Athlon (which we will see).
The one area where P4 should excel is in SSE2 optimized floating point math intensive applications, which is why Intel are now trying to reposition the P4 as an Internet/multimedia CPU rather than a general purpose one. The fallacy of this is that once you can decode your DivX in real-time, you don't need to go any faster!
You've missed the point again. Please.
You say "it _is_ the first overhaul by Intel"
I say "it's _not_ an overhaul".
My introduction of the other companies into the argument was simply (blimey, I add things to simplify my argument and I start losing people) to indicate what a "complete architectural overhaul" _really_ means.
If my statement is correct, that the change does not classify as a "complete architectural overhaul", then your, and the original statement are vacuously false as they refer.
Do people not learn logic and grammer any more?
Reread what I posted; see what I put; unravel the rhetoric of using sarcastic irony if you may; and condense what I wrote in your mind to 'Intel have not performed a "complete architectural overhaul'". It is there.
If you still don't get it watch the "he's got a knife" scene from Crocodile Dundee.
FatPhil
Also FatPhil on SoylentNews, id 863
If this doesn't outperform AMD's offering, then the parodies will be flying fast.
What you're missing is that the P4 is going to be a single-cpu part, so there's no reason to split up the bus. Even in a dual processor setup, each cpu isn't hitting the bus for it's full capacity anywhere close to 100% of the time unless it's running a loop or accessing memory that doesn't fit inside it's cache, in which case the software design is holding it back more than the system bus anyhow.
I don't think that many users would ever notice the difference, and intel probably can't afford to design it's next consumer level chip around a few percent of the market.
Worse: cold fusion. Guess their server needs more deuterium, or fantasium, or something.
---- ----
Napster-to-go says "Fill and refill your compatible MP3 player", which is a lie. It's not MP3. It's WMA with DRM.
Mainly because only part of the chip is running at that speed, not the whole thing.
Hmm, it's there at the bottom of the page:
So, yes, you are right: they don't support SMP so why would they split the bus?
But I question your "intel probably can't afford to design it's next consumer level chip around a few percent of the market" comment.
First of all, if Intel can't afford it, who can?
But more to the point: Is it really only a few percent of the market? I've just ordered a dual PIII and I selected the chip specifically because I could get SMP support. Does anybody have any statistics on single- versus multiple CPU PIII systems shipped? Is it really only "a few percent"?
Hi!
From the CNET article:
> The chip also comes with 144 new multimedia instructions for better graphics and sound.
I'm weeping! I *know* that they're multimedia instructions and so on, and probably really useful, and that people aren't hand coding this stuff... but doesn't anyone else think this is ugly?
Whatever happened to RISC?
Mike.
Tales from behind the Lagom Curtain
Basically, damn near no one runs a multiproccesor box. I know because I HAVE run one for the past 2 years: Intel puts SMP on a very low priority, and software designers do too. For example, there is only one MP3 encoder (gogo) that can even run with multiple threads. At a lower level, the ONLY operating system I haved used that even comes close to making good use of SMP is BeOS.
Bottom line: It would be a major disadvantage if the world would just wake up and start making SMP more practical, but unfortunatly, even Linux has not helped that much.
I just found the URLs I wanted. These people make QDR memory and these people make the controller. Now this is SRAM memory, not DRAM, but I don't think it would be too hard to make a mobo that took this, couldn't be anymore expensive than RAMBUS could it? Plus the controller has a sustained thoughput of 7.2GBps at 100MHz, WOW!!!!!
The world really is round and aliens are not stealling your socks...
NetBurst - Intel
LightPipe - SGI
AMD has their flavor
Who's the best?
"a powerful and unexpected ally..."
I get a filter-errormessage when I try to access that page, and i'm not running any filter, so it seems their server has b0rked already.
:)
hmf, slashdotting is to powerfull.
--
"Rune Kristian Viken" - http://www.nwo.no - arca
I am tired of seeing Intel put out more and more vaporware. RDRAM, IA-64, etc, etc... I don't know of any other chip maker that puts out so much vapor. AMD's chips did what they were intended to do. DEC (compaq) Alphas haven't failed yet, (supposed to be 1.5GHz+ by the end of the year.)
I am willing to bet that AMD will have a 64-bit arch out (mainstream) before Intel.
IA-64 has 1/5 the performance of an alpha under gcc, which is not optimised for the alpha. (likely the kind that is 3x an Athlon or more for a P3)
Even a 2 year old alpha can beat most P3s (1.5 -2x P3 MHz = alpha MHz in performance)
Another thing 550 P-3 $159, 600 Duron $99 (or 109, can't remember exactly). Duron is not 2/3 a P3's performance. Is Intel too greedy? In SV, I talked to an Intel CAD engeneer and he said as long as it sold for a 24 or 26% profit Intel would make anything. I wonder what AMD's profit level is.
btw anyone ever looked at Alpha vs Intel's touted FP performance? hint, Intel is in the dust.
Whose tech sharing with DEC resulted in Intel employing such Alpha features as Branch Prediction without license and a 12 count complaint filed against Intel. All very interesting stuff.
Vote Naked 2000
A feeling of having made the same mistake before: Deja Foobar
I have a PIII 500 on a 440BX board. I've been waiting for Intel to give up Rambus and make a high-end chipset with AGP4x and slot1. Is this a lost cause? If so, I'll probably wait until either:
Rambus gets off their high horse and lowers the prices;
Rambus drops their royalties;
Something beats Rambus; or
The Athlon-Killer arrives
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer
And if not then which "local filter list" are they referring to?
The only Good System is a Sound System
duh. is it just me, or is this just a load of crap. with the incredible tech available right now in 3d video cards, which are getting better all the time and will probably hit the ceiling pretty soon, why would any home user want 3d on their cpu? for the extra cash it would cost to get this feature, i'd rather spend on a kick-ass 3d card. cut the crap with all this hardware bloat and just give us a fast reliable chip! oh, and a motherboard with a reasonably fast bus would be nice as well, but let's not get started on that one...
Sweet! I've been waiting for features like that forever! Thanks Intel and thanks CNET! You guys rock!
CNET:
"The chip [...] represents the first complete architectural overhaul of the company's processor line since 1995, when the original Pentium emerged."
Erm. I've programmed for z80, 68K, Arm, C80-MP, H8, PPC, Axp, Sparc, HP-PA and the ubiquitous x86 (all varieties).
If the Pentium is a "complete architectural overhaul", then what the blazes does one call the Vax->Axp change, or the 68K->PPC change, or the C80->C6000 change?
Some people live in very sheltered worlds, evidently.
FatPhil
Also FatPhil on SoylentNews, id 863
Considering the P4 only does a single proc config...
A deep unwavering belief is a sure sign you're missing something...
I heard the "Burst" part refers to the little puff of vapor that you get with each press release.
--
Sheesh, evil *and* a jerk. -- Jade
Simple, you don't quad pump. The so-called quad pumped SRAM I have seen have 2 busses: one for reads and one for writes, or if you prefer one input and one output pin per data bit.
This avoids bus turnaround times and there is AFAIR a single address bus which is running slower since the data is transferred mostly by bursts on one or both of the data buses. As long as you can place 2 address/command cycles in the duration of a data burst, you are limited by the bandwidth of the data busses.
Actually this only doubles the bandwidth for some kinds of workloads but not for others: if you are performing statistics computation on a large set of data, you only read from memory and it becomes equivalent to a DDR bus. I suspect that this is what would happen to my workloads: analyzis of large amount of data to extract faint signals from noise with a read to write ratio between 1000 and 1000000.
It would be silly to quad-pump a bus in frequency: if you can afford x million of transitions per pin on the data bus, halving the number of transitions on the clock line(s) would not simplify the design nor measurably reduce the noise and radiated energy.
Is it just me, or is the name not necessarily just superflous?
1) The P4 has very long pipes.
2) The P4 has small caches.
3) The P4 has huge bus bandwidth.
4) The regular FPU has been largely depreciated in favor of SSE2.
What does all this add up to? A chip to accelerate 3D. This feature list reads largely like the list of the Playstation 2. (Aside from the long pipelines thing.) You've got the small caches, high bandwidth, and the vector pipes. My guess is that Intel, seeing NVIDIA cramming more and more into the GPU, is trying to come back and troughly blow them out of the water. This chip might process slower per clock for many uses, but the high clock makes up for that. On the otherhand, things that are extermely regular without any branches (ahem, 3D geometry processing) will absolutely fly through this thing.
A deep unwavering belief is a sure sign you're missing something...
How about a filter that tracks referrals from Slashdot and bounces them beyond a certain load level ?
I've no idea if that's what happening, but it's something I'd want to have on hand, if I ran a site like Anand that was regularly whacked with Slashdot's million typoing monkeys.
so it'll be as much faster as when I put the 387 into my 386?
da w00t.
da w00t. mtfnpy?
Speaking of The Reg, has anyone deciphered the (il)logic behind the ordering of their articles on the page? Usually it seems that they push new articles down from the top, but sometimes I see articles further down which I have not seen before. And older stories with previously clicked links occasionally reappear at the top.
--
Sheesh, evil *and* a jerk. -- Jade
is why this marketologs refused to call it "2GHz processor" because of this "Rapid Execution Engine"?
---
Every secretary using MSWord wastes enough resources
I don't know about the rest of you but i don't have enough bandwidth for the text based internet as it is.(It really suck living at the end of a copper line, Max = 26.4 kbps)
In addition, the Pentium 4 will contain a 20-stage pipeline. The pipeline is a processor's assembly line. While this means the Pentium 4 will have a line twice the length of the 10-stage Pentium III, the longer pipeline will create room for speeding up the chip.
Could someone explain to me how having a longer pipeline speeds things up? this seems kinda counter intuative to me. Guess its like the pipelines in the 3D GPUs, but i don't see how that would work in a general purpose CPU.
It will contain 42 million transistors, compared with 28 million for the Pentium III.
Even with a smaller feature size won't this create a lot of heat, especially running at 1.4Ghz? IANAExpert but since PIII's run at 90C can we expect this CPU to run ultra hot as well?
Those who will not reason, are bigots, those who cannot, are fools, and those who dare not, are slaves. --George Gordon Noel Byron (1788-1824), [Lord Byron]
Um, I don't know if you're serious, but stuff like this works perfectly fine on earlier CPUs too, of course. ;^) I probably shouldn't be doing this, but Cycore have some neat tech for doing this. According to their download page, the plugin for their technology (Cult 3D) is available for Linux as well as the Other OS...
main(O){10<putchar(4^--O?77-(15&5128 >>4*O):10)&&main(2+O);}
-- Sig (120 chars) --
Your friendly neighborhood mIRC scripter.
* Q
P.S. If you don't get this note, let me know and I'll write you another.
i'm actually plesantly surprized... looks as if intel put alot of planning and time into this. as soon as there is a p4 sdram option i'll look into picking up one of these suckers...
Another processor from intel? Now damn't I just
gave them a bunch of cash for the PIII, just
like I did the PII, and just like the Pentium and
the Pro version.
I didn't really notice a big jump in performance
on the last buy, but what can I do...it is intel.
Why is this so difficult for people to understand? Unless you are doing something really hardcore, like lots of video work or heavy numerical analysis, you're not going to notice any performance benefit. Additionally, we've reached the point where rethinking or rewriting can pay off much, much more than incremental processor speed upgrades. For example, Borland's Object Pascal compiles 10-100x faster than gcc. If you use it, then you're getting an order of magnitude increase. Compare that to the benefit gained by going from a 400MHz Pentium II to 1GHz Pentium III (less than 3x).
Then what do you suggest, That Intel and AMD simply pat each other on the back and close up shop? "Yep, we made it to a gigahertz, and no one needs anything faster than that so we can convert all of those fabs into hydroponic potato farms..." ;-)
Every next core that the two of them come out with has a few neat tweaks inside, but they are minor. It's pretty hard to come up with an earthshattering new archiecture every few months.
If you feel pressured to buy a new PC every year, get a different hobby, or get counseling.
Since when did people accept, without question, WITHOUT QUESTION, that they need to spend $2k on a new PC every 1-2 years!? To me, that is absurd. When did the brainwashing happen? How did we all miss it without doing anything?
Or is this just what it's like to live in on an exponential curve?
---
Unto the land of the dead shalt thou be sent at last.
Surely thou shalt repent of thy cunning.
https://www.accountkiller.com/removal-requested
Hell yeah! I second the motion. All they do is dis big companies, call everything hype, but never have much to say that is informative. They are like the Enquirer of Technology. Occasionally, getting info quicker than the mainstream, but usually their articles are trivial, mindless bullsheet.
JOhn
Campaign for Liberty
On the other hand, note that Merced/Itanium/IA64/whatever seems to have gone away. The Register now points out that IA32 is 2x faster than IA64. Oops. Probably just as well; Merced was hell to program. VLIW architectures require miracles from the compiler.
Besides, even the 1GHz PIII is mostly vaporware. Try to get one. Yes, they exist, but there aren't many of them.
It seems that way, but in practice, modern x86 CPUs (Pentii, Athlons, Crusoen) are just the x86 instruction set wrapped around something which is not like an 8086....
Fixing copyright
Another processor from intel? Now damn't I just
gave them a bunch of cash for the PIII, just
like I did the PII, and just like the Pentium and
the Pro version.
I didn't really notice a big jump in performance
on the last buy, but what can I do...it is intel.
Of course most of us really don't need this new
processor...but we are going to buy it anyway. We
are going to do what Intel tells us is the right
thing to do...what we are told we need to do.
Where we fall short...Intel will tell the OEM's
about how they need to switch to this new
processor...because all of the older and cheaper
ones are really tough to make now. It is really
tough to make the older processors because they
don't make as much from them as they do the new.
Granted my views are a bit twisted, but
one has to admit there is part of a truth
here.
"You should always go to other people's funerals; otherwise, they won't come to yours." -- Yogi Berra
Sorry, I'm far from a RISC purist, but we have an issue:
1) Functionality costs chip real estate
2) Speed costs chip real-estate
If we start doing the graphics and the sound on the CPU, great for a notebook, but isn't that processor going to perform wose than an equivalent lower functionality chip? I do not object to buying a clever sound card or graphics card should I need one. If I don't, then I can live with something more basic and leave the CPU to do what it does best.
Why compete with peripheral vendors, unless you are really going for the single-chip that does everything market?
The Register has a nice anti-hype article about the P4.
My favourite is
Hi!
something is borked.
Thank you for answering my question, of whether anandtech was dead, or if my employer had attempted a transparent proxy and failed.
----------------------------
Were you actually planning on reading the article before speculating wildly?
You must be new round these parts...
I always read the articles first - don't you? :)
--
"Rune Kristian Viken" - http://www.nwo.no - arca
Hmmm... I wonder if their webserver is running on a Pentium 4?
...that would be a Red Hat.
I'm really surprised about this pentium 4 chip.
Didn't Andy Grove write a book called "only
the paranoid survive"? I guess the paranoia
is over and pride is calling the shots:
to wit:
1.) dual RDRAM channels? RDRAM? McFly? Hello?
RDRAM is dead. I don't care if it's the same
price as SDRAM. Nobody in their right mind
is going to commit to rambus based PC's. Intel
and rambus tried to force a new standard down
the collecive throat of the industry. Just
like the old IBM and the microchannel it has
failed. Just like IBM of old this attempt
will come back to haunt it for a long time.
2.) No SMP? You must be kidding. Intel's SMP
architecture was the only thing separating
it from AMD. Now intel is producing chips
that are incapable of SMP? puh-leeze. Does
the word scalability mean anything to these
people? If pentium iv ships with any less
than 4-way SMP it will be a critical error.
3.) More cpu instructions? How many instructions
does the ia32 architecture support now? 500?
And what are these new instructions going to
buy me? VR on ebay? come on. If I want high
performnce 3d i'm going to buy a video card
not a franken-cpu. Intel is going off the
deep end with their bizarre and shallow
marketing. Maybe they can sell these chips
to the 10 people on their Web Outfitter
service. A sucker is born every minute but
they aren't the consumers of high performance
CPUS.
In the end we have intel, formerly one of the most
entrepreneurial and forward thinking companies
of our generation being replaced by a prideful
monopolist that believes the market will buy
anything that it produces.
Intel has the most aggressive competition of
the last 15 years to deal with and they are
doing little more than putting their heads in
the sand. I predict they will lose 20-40% of
their market share withing three years if mistakes
like this one (and the mistakes-in-waiting of
the ia-64) come to pass.
AMD and Transmeta are going to use
this fiasco to pierce intel's armor.
how many OEMs will they be able to steal away?
Do you think Dell and compaq want to sell
high performance computers with no SMP support
and overpriced RDRAM? They know the market will
not forgive them if they try.
Intel might be king of the hill today but
in the end goliath is about to be cut down
with his own tools.
Where have you gone Andy Grove? your ship
is sinking.
--chuck
At the very core of the Pentium 4 lie the Arithmetic Logic Units (ALUs), the main integer units of the processor. Intel marketing spiced up the naming of the faster ALUs by calling them the "Rapid Execution Engine," also a fitting name for Texas :) This sounds just like a math co-processor for the 386, only integrated. Oooooh, Aaaaaahhh!
Hehehehehehehehe......Shrub the Little Bush
400MHz System Bus
The fastest Pentium III available is designed to work with a 133MHz front side bus (FSB). With approximately 1GBps of bandwidth, this FSB acts as a bottleneck between the CPU and the rest of the system. Intel will remove this bottleneck with the Pentium 4 by using a 100MHz FSB quad-pumped to the equivalent of 400MHz. 400MHz on a 64-bit bus yields 3.2GBps of data bandwidth, three times what the Pentium III's 133MHz FSB can handle. This bandwidth will keep the CPU well connected to the i850 chipset, codenamed Tehama, which will support dual RDRAM channels. :( that crosses this processor off my wish list, maybe you can still stomach RAMBUS. Why pair this processor with RAMBUS when you could pair it with Quad Data Rate Dram, I know its out there I just don't have the URL on hand, someone help me out here.
All this hub-bub about the 400Mhz bus and now I find out that they are still using RAMBUS
RAMBUS would make a good name for a clown.
One Instruction (Set) Computer has one instruction:
Subtract operand X from operand Y and if zero jump to location specified by operand Z.
Or something like that (the 'if zero' bit is the bit I'm not sure about).
Provably Turing complete.
Also FatPhil on SoylentNews, id 863
Works for me - here is the summary:
More at http://www.anandtech.com/showdoc.h tml?i=1301&p=2.
Hi!
www.anandtech.com
www.anandtech.com is running Microsoft-IIS/5.0 on Windows 2000
Microsoft-IIS is also being used by Nasdaq, The National Football League, and Intel. Windows 2000 users include Microsoft, The Nasdaq Stock Market, Hotbot, BigCharts, and Dell.
Yes, but whats that got to do with the price of tea in D'ni?
How do you "quad-pump" a clock? Sampling at both edges gives you a "double-pump", but where do you get two more samples..? Do you just run a second clock at 1/4 period off-phase? What's the advantage of that over running a 2x clock?
Never underestimate the bandwidth of a 747 filled with CD-ROMs.
The article says:
Hi!
Some people would have us believe that.. *grin*
Maybe they're still working on a click-through NDA...
Gav
"There's no such thing as data that can't be manipulated"
From the article:
IANACD (I am not a chip designer), but this seems to me like a major disadvantage compared with the Athlon. Am I missing something obvious?
Hi!
We just saw a story claiming that Intel was scaling back on Rambus specifically that "Until last month, Intel had promised that RDRAM would be the exclusive memory for the Pentium 4 (P4). Now an undefined SDRAM memory (probably PC133 or DDR) will be used in its place." That article claimed that there would be 3 sdram chipsets. Now it seems to be undefined... I would have figured that an sdram chipset would be available first to encourage adoption of the p4. Rdram was only supposed to be for the very highend desktops. Just my 2 cents.
Try this link at CNET for more information.
---
Jon E. Erikson
Jon Erikson, IT guru