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It's not x86 compatible. It's a MIPS64 clone. According to this, they'll use binary translation and extra instructions to run x86 binaries.

http://www.pldesignline.com/news/210201111

Both the four- and eight-core versions of the Godson-3 are implemented at 65 nm, with clock speed of 1GHz. The design features a distributed, scalable architecture with reconfigurable CPU core and L2 cache. The devices are designed for low power consumption - the four-core draws 10w while the eight -core draws 20w, according to Xu's presentation. The designs utilize MIPS64 cores with more than 200 additional instructions for X86 binary translation and media acceleration.

Problem is it's unlicensed, so they would most likely be sued for patent infringement if they sell it outside China.

http://www.mdronline.com/watch/watch_Issue.asp?Volname=Issue+%23072505&on=1

In December 2003, Advanced Micro Devices and BLX IC Design announced a relationship and opened the AMD/BLX Computing Client Development Center in Beijing. BLX IC Design is creating reference designs for thin clients and other computing products using AMD and BLX IC Design processors. The first two products are thin clients powered by AMDâ(TM)s MIPS32 - compatible Alchemy Au1500 processor and BLX IC Design's Godson-1. The creators of the Godson-1 say its architecture is "MIPS-like" - a description that annoys MIPS Technologies, which doesnâ(TM)t authorize the Godson architecture or license any intellectual property to ICT or BLX IC Design. AMD, which is a MIPS licensee, says it encourages BLX IC Design and MIPS to resolve their licensing issues.

Lexra tried to sell unlicensed MIPS clones and was effectively shutdown by lawsuits. As this Lexra guy puts it -

http://jonahprobell.com/lexra.html

It has been interesting to watch as the Chinese company, BLX, has made and sold powerful processors in China that execute MIPS-based instruction sets. BLX is legally and morally clear of violating MIPS Technologies' patents. BLX has chosen not to pay anything to MIPS Technologies while a host of American companies with their own powerful MIPS instruction set processors pay large sums of money to MIPS Technologies for the privilege of not being hassled by lawsuits. After its experience with Lexra MIPS Technologies changed all of its 32-bit cores to ue its new MIPS32 instruction set which extends the MIPS-I instruction set to include other features patented by MIPS Technologies. This is similar to Intel's addition of the MMX instruction set extensions to Pentium III in order to prevent AMD from building compatible processors.

Quoting from http://www.mdronline.com/watch/watch_Issue.asp?Vol name=Issue+%23022007&on=1
Freescale wins an MPR Analysts' Choice Award for MRAM (magnetic random-access memory). Freescale's MR2A16A is the first commercially available memory chip based on spintronics technology. (See MPR 2/20/07-04, "MPR Innovation Award: MRAM.")

  I'd say a few people, if http://www.computerworld.com/hardwaretopics/hardwa re/story/0,10801,83987,00.html is considered sane.

It's not a new technology, but from the article, they seem to have made some improvements. Maybe you should try reading it?

Despite the fact that reverse engineering is legal for plenty of abstract instances, there's only a few cases where it's legal (in the US) to reverse engineer to compete/modify/upgrade (with) a product.

Is this like the "Security Measures" in the PIII http://www.mdronline.com/mpr_public/editorials/edi t13_02.html/ Remember the uproar that caused?

why not .. everybody else is doing it

Sony originally promised the PS2 could render 75M simple polygons per second, but also said the geometry engine's limit was 36M polygons per second. This figure is accurate, but like all such numbers in the graphics industry, it is achievable only in a single-function demo app. Such figures are useful only for comparing the raw performance of different designs.

Sony never claimed the PS2 could support HDTV resolution. The company was very clear about the limited frame-buffer memory on the Graphics Synthesizer chip.

Sony did, in fact, make a multiprocessor PS2-based workstation, the GSCube, which combined 16 complete PS2-compatible subsystems. The "Graphics Synthesizer I-32" chip used in this system had a 32MB HDTV-sized frame buffer, leading me to speculate at the time (August 2000) that Sony would soon introduce an HD-capable PS2. They could have, but they never did. I can't get 'em all right, I guess. They demonstrated to me (personally) this system rendering scenes from the Final Fantasy movie in real time, so that wasn't hype either.

Here are the Microprocessor Report articles I wrote at the time (subscribers only):

http://www.mdronline.com/mpr/h/19990419/130501.htm l

http://www.mdronline.com/mpr/h/2000/0821/143402.ht ml

. png

Sony originally promised the PS2 could render 75M simple polygons per second, but also said the geometry engine's limit was 36M polygons per second. This figure is accurate, but like all such numbers in the graphics industry, it is achievable only in a single-function demo app. Such figures are useful only for comparing the raw performance of different designs.

Sony never claimed the PS2 could support HDTV resolution. The company was very clear about the limited frame-buffer memory on the Graphics Synthesizer chip.

Sony did, in fact, make a multiprocessor PS2-based workstation, the GSCube, which combined 16 complete PS2-compatible subsystems. The "Graphics Synthesizer I-32" chip used in this system had a 32MB HDTV-sized frame buffer, leading me to speculate at the time (August 2000) that Sony would soon introduce an HD-capable PS2. They could have, but they never did. I can't get 'em all right, I guess. They demonstrated to me (personally) this system rendering scenes from the Final Fantasy movie in real time, so that wasn't hype either.

Here are the Microprocessor Report articles I wrote at the time (subscribers only):

http://www.mdronline.com/mpr/h/19990419/130501.htm l

http://www.mdronline.com/mpr/h/2000/0821/143402.ht ml

. png

The details of the CS301 are supposed to be given at Microprocessor Forum 2003, this week. I think this would indicate a little more substance to the chip. Especially since ClearSpeed wil have to defend their claims to experts in the industry.

Peter Sandon, Senior Processor Architect, Power PC Organization,
IBM Microelectronics IBM is disclosing the technical details of a new 64-bit PowerPC microprocessor designed for desktops and entry-level servers. Based on the award winning Power4 design, this processor is an 8-way superscalar design that fully supports Symmetric MultiProcessing. The processor is further enhanced by a vector processing unit implementing over 160 specialized vector instructions and implements a system interface capable of up to 6.4GB/s.

Found it... RAMBUS snuck around the JEDEC committees working on SDRAM and failed to mention some vital patents it held. I still don't know how it turned out, tho, but RAMBUS got hit with some heavy lawsuits as a result.

Take a look at this baby, ibm's new power4. They are putting two 1GHz-cores on one proc. My uninformed opinion is that apple should have gone with IBM instead of motorola.
Btw. Microprocessor Report is a cool, professional magazine and if you browse around their site you'll get a good overview of what's out there in the world of cpu's besides P IVs and thunderbirds.

For anything up to 8 CPU's, Intel hardware will be better most of the time. That covers all small servers, departmental servers, web servers, small/medium database servers and a stack of other stuff. Sure, 8 CPU intel machine's aren't great, but then 4 CPU ones go as fast as 8 CPU Suns.

All Socket A Athlons and Durons are multiprocessing enabled. They only require a new chipset to do so. AMD is developing the 760MP for this purpose. It will also support DDR SDRAM. This topic will be discussed in much detail at the Microprocessor Forum next week. VIA may or may not develope a multiprocessor capable chipset for AMD processors. Hotrail was developing a chipset that would support 4 and more processors, but they dropped the project. I'll be covering all news of the 760MP next week at AMDZone, and expect Tuesday to be the big news day if you are interested in the 760MP. There should be a load of new information, and possibly a press release or two.

20 stage pipelines are not a good solution. I betthe BPU itself is about half the size of the whole processor. Forget 98%. The BPU better be 99.999% right at prededication of the williamette will have scky performance.

Check out this article at MDR.
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The five stage pipe used by PPC has to stuff a lot more work between clock edges so it will never catch up in clock rate to a modern microarchitecture desktop CPU.

It's all about tradeoffs. The short G3/G4 PowerPC pipeline limits the clock ramp, but it sure makes for much faster branch recovery on a mispredict. The Pentium Pro/II/III architecture only makes up for its longer pipeline by expending much more effort on predicting branches (and the work goes on: at least two papers in this year's ISCA conference from Intel research groups which work on branch prediction-related techniques).

Moto/IBM get to expend less chip area on all these expensive prediction techniques, have a much simpler pipeline, and hence get smaller, cheaper chips which use less power (advantageous when you look at Intel's problems putting their high-speed Pentiums into laptops).

On the other hand, it's hardly as though Motorola/IBM are ignorant of the advantages of superpipelining. You can bet your bottom dollar that the Power4 (design goal = 2 CPU core @ 1GHz) has more than a 5 stage pipe, and Motorola is about to announce the details of the G5 pipeline in three weeks at the Microprocessor Forum.

Check out the first day's sessions.

The Register is reporting a rumor that AMD has hired a top Alpha engineer to guide the development of the 64bit K8 which may be demo'd as soon as the Microprocessor Forum early next month in San Jose.

MAJC home page . See the docs home page - introduction, and a "community" page .

They haven't really released enough details (on their website) just yet, but it does look interesting. One of the more obviously different attitudes the specification takes is highly customisable implimentations - you design a variation targeted at a particular application, whatever that might be - graphics accelerator, MP3 player/decoder, MPEG2/DVD decoder, or a more general purpose chip. Since it is mostly being targeted at embedded applications this is not surprising though.


Some other interesting aspects include:

'Support' for JIT/access-time compilers - not only does this help Java, but it is to make backwards compatability with older versions quite simple. This seems a bit like what Transmeta are doing, which was co-founded by an ex Sun guy btw.

Hardware support for ultra-fast thread switching - so fast that if one thread stalls waiting for DRAM access (which can take up to 100 clock cycles), you can switch to another thread rather than go idle. On many current OSs threads will be switched if the current one has to do some slow I/O say (ie read from disc) - so this is quite an improvement.

A more general approach to improving parallelism - you can have more than one CPU core in a single physical chip, which might or might not share their 1st level caches. (read this Microprocessor Report article for some background on this.) IBM are apparantly going to do a version of the PowerPC G4 which has 2 CPUs on one core, and I kinda suspect Sun might be planning something similar for their UltraSparc-V.

I'm not sure how Sun plan to make money of the design. It seems pretty likely they might do something like their "community source" model - you can get the design for free, but if you want to use it commercially you pay a license. ARM is doing well just licensing their CPU designs. I'd image Sun using to 'assist' their servers as add-on boards for doing heavy multi-media/3D graphics stuff - can you say "render farm"? Also, since Sun like selling their servers, they'd be happy for people to make lots of little, cheap devices that connect to nice big Sun servers.

Like the original poster said, IEEE Micro will probably have some interesting stuff, but it seems Sun aren't releasing all the details yet - looks like we'll have to wait until the Microprocessor Forum in October. I liked the article (written by the Sun engineers) about the UltraSparc-III - not only was it interesting (and I like Sun's approach) , it helped me figure out the inherant problem with the IA-64 architecture...