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At least this year it was awarded to the correct three people.

https://semiengineering.com/wh...
https://www.chemheritage.org/d...

That's not true; GPUs basically always use the latest process technology available, just like CPUs. Recently, there have been some degenerate cases where a new process is (at least initially) slower and more expensive than the previous one; but in general, they always move to the latest and greatest process, once that process is capable of making a better product.

As for die size, the big GPUs are way bigger than CPUs. A 22-core Xeon Broadwell E5 from 2016 is 7.2 billion transistors, and 456 mm^2. The NVIDIA GP100 chip (also 2016) is 15 billion transistors, and 600 mm^2. The AMD Ryzen (2017) info I can find says it's (probably up to) 4.8 billion transistors.

I have no idea what you mean by "tolerances". Maybe you mean "process variation", which is a natural part of any semiconductor manufacturing - and is controlled by the fab (TSMC, GlobalFoundries, Samsung, Intel), not the chip designers (Apple, NVIDIA, AMD, ummm Intel again). The design houses ship off the chip they want - and the fab produces it, with some chips a little hotter/faster than others. Over time, they can tighten up the process so it has less variation and higher yields, but nobody is "running wild" with anything.

It's complicated too, because the node names are really just marketing hype. Just as "Kaby Lake" is a name that Intel gave to a collection of optimizations put in a single chip, or "Pascal" is a name that NVIDIA gave, or "Ryzen" is a name that AMD gave – 14 nm is a name that some fab gives to their latest collection of optimizations. There's no one measurement that corresponds with the marketing name any more, like there was until the early 2000s. [citation] The upshot of this is that Intel's 14 nm isn't the same as TSMC's 14 nm or GloFo's 14 nm, so you can't necessarily compare them. Intel does generally have an advantage in this space, however. That said, everybody pretty much uses the latest, greatest process technology available to them from the fab they have chosen. And it is often the case that a GPU is one of the first things manufactured in a new process at a fab, so they aren't benefitting from anybody prior - especially not at a different fab, because the fabs don't share their secrets, or even the same set of features (as noted previously).

Also, with a brand new process, yields can be very low, so a given company may choose to reduce their risk by making their first chip on a new process either a die shrink of a previous chip, a minor revision to an existing architecture (Intel's "tick"), or a small low-performance chip. Once the kinks have been ironed out on one of those "easy" options, they can shift the bigger, higher-performance chips to the new process. But in some cases, if they started out on the big chips, the yield would be 0% - or if not 0%, the cost of an individual chip would be so high that no consumer would ever pay for it.

And while I will grant you that GPUs have *less* cache, they do still have some caches and other memories. A GP100, for example, has 14 MB of register files, 4 MB of L2 cache, 3.5 MB of shared memory, and 1.3 MB of L1 cache. That's still well shy of the 22-core Xeon I mentioned earlier, which can have up to 55 MB of LLC, but it's a pretty good amount all the same.

The real reason that GPUs have always outpaced CPUs is because they are inherently parallel. In addition to all the architectural optimizations that are made every year, they also add more cores every year; while most of us are still using something in the vicinity of quad-core CPUs, just like we were 5 years ago. Also, the parallelism of GPUs means that they have more freedom for architectural changes to yield throughput enhancements. A CPU is largely targeted at single-thread performance, so most of the optimizations they make will enhance that. A GPU architect can make similar optimizations to enhance a single thread's performance, but they can also make changes that only help parallel computation.

So GPUs are arguably more advanced than CPUs, or at the very least on par with them - and they will continue to outpace CPU development for the foreseeable future as well.

Even flash memory improvements seem to be slowing down, but that may be that demand is huge and increasing.

No, charge storage scales even worse than switching—and everyone agrees. Flash has recently been kept on life support by staggering efforts in bit-error management.

Thus all the research funds right now (ST-MRAM, carbon nanotube NRAM, STT-RAM, CBRAM, not to mention Intel's new TMium) are being funneled into bulk resistive technologies, such as the chalcogenides.

The charge bottle is dead. Long live the fickle dendrite!

The problem with silicon was written about extensively in 2016 (this only a decade after the frequency free-lunch had already ended, and five years after the power-scaling free-lunch started being served up in Continental-breakfast portion sizes).

TSMC Plans New Fab for 3nm
Focus Shifts To Architectures
ITRS roadmap predicts end of process miniaturisation by 2021
Transistors Could Stop Shrinking in 2021
Alchemy Can't Save Moore's Law
Will 5nm Happen?
TSMC will begin 10nm production this year, claims 5nm by 2020

TSMC remains strangely bullish, but you also need to realize that line size is not what it used to be. It used to be they pretty much shrunk the entire lithography. Now they shrink what they can shrink, and then define the new lithography based on the skinniest resulting body part (problem: what's left to measure after the wrist? answer: a Taiwanese wrist).

Even flash memory improvements seem to be slowing down, but that may be that demand is huge and increasing.

No, charge storage scales even worse than switching—and everyone agrees. Flash has recently been kept on life support by staggering efforts in bit-error management.

Thus all the research funds right now (ST-MRAM, carbon nanotube NRAM, STT-RAM, CBRAM, not to mention Intel's new TMium) are being funneled into bulk resistive technologies, such as the chalcogenides.

The charge bottle is dead. Long live the fickle dendrite!

The problem with silicon was written about extensively in 2016 (this only a decade after the frequency free-lunch had already ended, and five years after the power-scaling free-lunch started being served up in Continental-breakfast portion sizes).

TSMC Plans New Fab for 3nm
Focus Shifts To Architectures
ITRS roadmap predicts end of process miniaturisation by 2021
Transistors Could Stop Shrinking in 2021
Alchemy Can't Save Moore's Law
Will 5nm Happen?
TSMC will begin 10nm production this year, claims 5nm by 2020

TSMC remains strangely bullish, but you also need to realize that line size is not what it used to be. It used to be they pretty much shrunk the entire lithography. Now they shrink what they can shrink, and then define the new lithography based on the skinniest resulting body part (problem: what's left to measure after the wrist? answer: a Taiwanese wrist).

What about physical access to device. Should the device contain the decryption key, so that it could be decrypted if the flash chip is removed?

The device always contains a decryption key... it's just a matter of how hard it is to get to... and it may not actually be located in flash memory.

Disassembly that might take a tech an hour or two?

Disassembly yes, retrieval, no.

What do you know about focused ion beam hacking? http://semiengineering.com/eve...

Short version: A reverse engineer can take a dozen or two chips of the same kind, slowly grind them down layer by later, selecting the best example of each level, then continue the process. Once you've gone through all of the layers you can actually construct a pretty accurate design of the internals. From there, you can use a FIB and some probes to actually get access to the inner workings of the chip.

Chip designers for years have to various extents attempted to take steps to prevent this. The one advantage they have is doing so is very difficult & expensive... but a successful hack can more than pay for itself.

I ask not for government but for other third parties. If you die should your spouse gave legal right to access your phone and encrypted storages?

Which is a fair point. If your loved one goes missing and leaves their phone behind, unlocking it to find out who they were recently talking with may be difficult if not impossible. If someone dies, your window to use their finger to unlock the device is quite short.

This is only a wider version of a long standing problem... as I don't know many people who make it a point to stash a BitLocker/TrueCrypt/etc keys to a safe spot that will be discoverable upon their disappearance or death, but secure enough that an angry spouse or law enforcement agent wouldn't be able to uncover.

It's not the end of silicon that's in sight. It's the end of the growth described by Moore's Law, ultimately the end of shrinking silicon devices

That's what I was referring to implicitly, but it's also highly likely that silicon devices will be supplanted with III-V's or something else. 1.5nm seems to be the optimistic guess for the end of the line right now, and that's roadmapped for around 2021. 7nm is already dubious and it's slated for around 2018. See e.g. semiengineering.com/will-7nm-and-5nm-really-happen

It the end of civilization as we know it, depending on how many friends in the semiconductor business you have...

I think we've been fortunate to have Moore's law growth continue for so long, so that now we don't really need faster devices. Our current computers and even mobile devices are entirely capable of handling the mass consumer's needs. So while it may not be the end of civ, it's the end of an era where doubling came easy. And the end of silicon (ie the continued shrinking of silicon-based transistors) is pretty much within the next 5-10 years. Which is why physics (solid state physics), including e.g. topological insulators, is so important right now, if you're looking beyond those 5-10.

I'm not sure why they used K as the unit of measure, but I think a good one to consider is the number of monolayers of Silicon, which is the base material (and the substrate). The layer spacing in Si is about 0.27 nm, so 7nm is in the neighborhood of 25 monolayers. And that's across, mind you; thicknesses are around 1.2 nm (5 monolayers).

What interests me here is that IBM is hesitating at saying anything about going lower than 7nm. That appears to be the standard sentiment in the industry. Some are doubting even 7nm will be obtainable, while others are already planning for 1.5 nm. What's clear though is a lot of uncertainty about the very near future, and that we're about to hit bottom for current transistor technologies.

Whether or not it will happen is uncertain, but for now at least we're vaguely roadmapped to 3 nm by 2021. If 3 nm isn't the bottom, tho, it's very close, at only 11 monolayers of Si.

IBM is playing this exactly right. What we're looking at within the next 5 years, probably, and definitely within the decade, is a total shakeup of the hardware landscape, to be determined by the design of fundamentally different devices. R&D spending won't guarantee the winner, because it's still a pretty wide-open field, but it's something IBM must do.

I'm not sure why they used K as the unit of measure, but I think a good one to consider is the number of monolayers of Silicon, which is the base material (and the substrate). The layer spacing in Si is about 0.27 nm, so 7nm is in the neighborhood of 25 monolayers. And that's across, mind you; thicknesses are around 1.2 nm (5 monolayers).

What interests me here is that IBM is hesitating at saying anything about going lower than 7nm. That appears to be the standard sentiment in the industry. Some are doubting even 7nm will be obtainable, while others are already planning for 1.5 nm. What's clear though is a lot of uncertainty about the very near future, and that we're about to hit bottom for current transistor technologies.

Whether or not it will happen is uncertain, but for now at least we're vaguely roadmapped to 3 nm by 2021. If 3 nm isn't the bottom, tho, it's very close, at only 11 monolayers of Si.

IBM is playing this exactly right. What we're looking at within the next 5 years, probably, and definitely within the decade, is a total shakeup of the hardware landscape, to be determined by the design of fundamentally different devices. R&D spending won't guarantee the winner, because it's still a pretty wide-open field, but it's something IBM must do.