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Some knowledge about multicore cache coherence here. You are completely right, Slashdot's summary does not introduce any novel idea. In fact, a cache-coherent mesh-based multicore system with one router associated to each core was presented on the market years ago by a startup from MIT, Tilera. Also, the article claims that today's cores are connected by a single shared bus -- that's far outdated, since most processors today employ some form of switched communication (an arbitrated ring, a single crossbar, a mesh of routers, etc).

What the actual ISCA paper presents is a novel mechanism to guarantee total ordering on a distributed network. Essentially, when your network is distributed (i.e., not a single shared bus, basically most current on-chip network) there are several problems with guaranteeing ordering: i) it is really hard to provide a global ordering of messages (like a bus) without making all messages cross a single centralized point which becomes a bottleneck, and ii) if you employ adaptive routing, it is impossible to provide point-to-point ordering of messages.

Coherence messages are divided in different classes in order to prevent deadlock. Depending on the coherence protocol implementation, messages of certain classes need to be delivered in order between the same pair of endpoints, and for this, some of the virtual networks can require static routing (e.g. Dimension-Ordered Routing in a mesh). Note a "virtual network" is a subset of the network resources which is used by the different classes of coherence messages to prevent deadlock. This is a remedy for the second problem. However, a network that provided global ordering would allow for potentially huge simplifications of the coherence mechanisms, since many races would disappear (the devil is in the details), and a snoopy mechanism would be possible -- as they implement. Additionally, this might also impact the consistency model. In fact, their model implements sequential consistency, which is the most restrictive -- yet simple to reason about -- consistency model.

Disclaimer: I am not affiliated with their research group, and in fact, I have not read the paper in detail.

Besides the open-source, how is this project any different from what Tilera already has? http://www.tilera.com/

The seminal paper proposing the use of switched/routed interconnection networks on-chip (NoCs) was published by Dally and Towels 11 years ago in DAC'01: Route packets, not wires: On-chip interconnection networks. The idea of associating a router to each core and replicating it in "tiles" is not new either; Tilera was (IIRC) the first company to sell processors based on a tiled design, which was an evolution of the RAW research project. A related research project, the TRIPs, replicated functional units on each tile, rather than full cores. Intel has used a tiled design in the Polaris, SSC and MIC (which includes the forthcoming Knights Corner).

So no, the idea of using routed interconnects is not new at all. In fact, after reading the linked article, turns out that 2/3ths of the text are introducing the idea, and the last section details the contributions: Two ideas developed by the group of Li-Shiuan Peh seeking to improve performance (by using virtual bypassing, a form of routing precomputation) and reducing power consumption (using low-swing signaling).

Writing code for video cards is much more difficult than most people think. On the other hand, if it's really a light weight, low CPU task that's just insanely parallel, check out http://www.tilera.com/ They don't pack a ton or horses, but they do have a pile of cores.

Tilera has had 64 and 100 cores for a while now.

"Tilera's primary product family is the Tile CPU. Tile is a multicore design, with the cores communicating via a new mesh architecture, called iMesh, intended to scale to hundreds of cores on a single chip. As of September 2010, shipping versions of Tile have 36 or 64 cores. The goal is to provide a high-performance CPU, with good power efficiency, and with greater flexibility than special-purpose processors such as DSPs. In October 2009, they announced a new chip TILE-Gx100 based on 40nm technology that features up to 100 cores at 1.5 GHz. Other Gx family members will include 16, 32 and 64-core variants."
http://en.wikipedia.org/wiki/Tilera

64 Cores
"TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[1] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz."
http://en.wikipedia.org/wiki/TILE64

100 Cores
"The TILE-Gx processor family brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market."
http://www.tilera.com/products/processors/TILE-Gx_Family

Why hasn't it occurred? Because powerful computing hardware has never been so cheap and abundant. That is the new, disruptive change. It still growing by leaps and bounds. You can already buy cards with 64 cores running linux and put them in your PC or robot. Mobile devices are already going multicore. Distributed machine learning is already a reality. Those things did not exist before. and that is why there hasn't been 50% unemployment due directly to automation. Forget Asimov and Bradbury, they did not foresee it. Try Marshall Brain instead.

Running Linux on a 48-core system is boring, because it has already been run on a 64-core system in 2007 (at the time, Tilera said they would be up to 1000 cores in 2014; they're up to 100 cores per CPU now).

And Linux is a Johnnie come lately compare to the commercial Unices You could have gotten a Sun Enterprise 6500 with thirty CPUs in 1998, and a Sun Fire 15K with up to 106 UltraSPARC III processors in 2002; the Sun Fire E25K did 72 dual-core UltraSPARC IV+ processors in 2004.

Multi-core is old hat for the non-Intel folk.

As Seymour Cray said: fast CPUs are easy, it's making fast /systems/ that's hard. You need good I/O to keep the CPUs fed.

Running Linux on a 48-core system is boring, because it has already been run on a 64-core system in 2007 (at the time, Tilera said they would be up to 1000 cores in 2014; they're up to 100 cores per CPU now).

As far as I know, Linux currently supports up to 256 CPUs. I assume that means logical CPUs, so that, for example, this would support one CPU with 256 cores, or one CPU with 128 cores with two CPU threads per core, etc.

Tilera Corp. already has CPU architecture with 16-100 cores per chip.
TILE-Gx family

Support for these is already being included in the mainline kernel.

Sounds like the Tile64 idea http://www.tilera.com/products/processors/TILE64, which basically is a massively parallel design where each individual core is relatively low power. For a gaming system I think this might be quite suitable - it should be more GPU than CPU dependent anyway.

The company website claims...

  64-bit VLIW processors with 64-bit instruction bundle
  3-deep pipeline with up to 3 instructions per cycle

I don't know how this could be considered ARM or MIPS-derived...

A better description might have been in this article...

The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation.

I think these guys are trying to bring back the concept, with 64 interconnected processing "tiles" on a chip.

"Build a USD1000 desktop workstation, port Debian Linux to run on it and let the geeks out there adopt it.

There is no better way to explore a device's capabilities than to let the market do it.

I want one for myself. I am tired of the x86 architecture."

Well, in fact they've done almost this. The thing does run Linux, and
they have developed a "TILExpress-64(TM) CARD" which is a PCIe expansion
card with one of these things on it along with a bunch of stuff.

http://www.tilera.com/products/boards.php

No word so far on pricing for that card or the development tools.

However, I have noticed something that is conspicuously absent from the
coverage of the chip so far - the details of its memory management, or
lack thereof. No word so far on how much memory it addresses or whether
it has the sort of memory protection that we've come to expect of modern
general-purpose CPUs. My guess is that what they have is an absence of
any traditional MMU, and badly written code is free to run rampant in
system memory. This is understandable in an embedded system.

Regards, Non.

Idle Tiles can be put into low-power sleep mode
http://www.tilera.com/products/processors.php

For those of you wondering about what their software will be like, here's some info on their Multicore Development Environment (MDE). http://www.tilera.com/products/software.php It's not the most info in the world, but it's a start.

here is a bit