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Anandtech Looks At 'Celeron 2'
Oscarfish writes, "Anandtech has the scoop on the new batch of Celeron chips hitting the market. They're more or less Coppermine chips with half the L2 cache removed, so you basically have a Coppermine core with 128K L2, a 66MHz front side bus, and FC-PGA packaging. A decent choice for the "Value PC" segment, he says, but not for performance machines. "
As I understand it, there is still 256k cache on-board (saving money in the design process), but half of it is disabled to differentiate it from the Coppermine PIII processors, where it's all enabled. Doing it that way would be cheaper than having a completely different fab, I'd think.
Performance-wise, the average Joe who buys a Celery-based system isn't going to overclock, and the overclockers are a small, but devoted group that will find a way to crank the processors up anyway. The multiplier locks on processors don't really stop overclockers, but they do help stop people from remarking the chips since there's no easy way to tamper.
On the overclocking front, interestingly enough, Athlons are actually pretty overclock-friendly, and the Golden Fingers cards that simplify the process are pretty inexpensive. I run my K7-600 at 750 and it was quick and easy.
Basically, the new Celerys are a pre-emptive strike against the AMD Spitfire CPU's, which replace the K6-2 processor family but use an Athlon core and bus. I think AMD will continue making inroads into the Celery target market, though - the box companies have been burned too many times by Intel of late to put all their eggs in one basket. Dell is the last Intel-only holdout and we'll see how long that lasts.
Depending on pricing, these new Celerys could be a pretty good bargain for the "enthusiast". I may check out the possibility of slapping one in to replace the PII-350 I have in my old Mandrake box at home.
- -Josh Turiel
-- Josh Turiel
"2. Do not eat iPod Shuffle."
Cache organisation is as important as size! The larger caches (512KB-1MB) seen on SS7 boards were often direct mapped. Do not compare these with two-way or four-way (Celeron) caches.
The problem is a direct mapped cache has only one place for each RAM location (repeating every cachelength). Say you have a program that accesses a memory location, then accesses one [cachelength] away. The first will be flushed from cache to make room for the second. And over again = thrashing. You won't generally be able to predict physical addresses because paging remaps everything.
Two way set associative caches are a big win. Every memory cell can go into _two_ cache locations. That way, an LRU algorithm is used to decide who replaces what, and recently used data is much less likely to be flushed.
I'm very pleased with Intel's P6 four way set associative caches. When comparing cachesize, I multiply size by associativity. So a 128 KB 4way cache is as good as a 512 KB direct mapped.
This is definietly an oversimplification. There are a few problems/OSes that can keep their entire working set in L2 cache. Then large direct mapped is a win. But they are rather rare compared to problems that exceed L2 and need to coprocess 2 or more data elements.
Why is Intel crippling the new Celeron with a 66MHz bus? I mean the P3 is already at 133 so the Celeron is at half the bus speed of the P3. The Spitfire on the otherhand, shares the Athlons bus speed and seems will be a better performer. We'll see how this affects performance and how soon Intel will change their minds on Celeron FSB speed. I'm recommending my friends get Athlon systems or iMacs depending on thier needs.
--
Don't lead me into temptation... I can find it myself.
Pentium, Pentium II, Pentium III, Pentium Pro, Pentium II Xeon, Pentium III Xeon.
I'm still a little surprised they didn't go with Pentium Value for the Celeron. I mean, they paid the hundred bucks for the trademark, and they'll be damned if they can't squeeze every last cent out of it.
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www.bp6.com reports that single-CPU's works okay on the BP6 with the Powerleap 370 to FCPGA adaptor, but not SMP. Although I wouldnt be surprised to see the adaptor tweaked for SMP real soon now
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What you say is completely on-target, technically. But technical details have nothing to do with the choice of cache size.
The 'new' Celeron, with another cache level is being introduced to add confusion to the market. It will be marginally cheaper than the larger cache version, so cost of production is not the issue.
In fact, this Celeron will probably start life as the larger-cached version, and have half it's cache disabled (intentionally destroyed) to offer the customer an ILLUSION of having more choices.
Intel has done this before:
386SX was a 16 bit 386DX. Valid difference.
486SX was a 486DX, with a non-functioning floating point unit. The DX chips that burned out their FPU during testing were relabeled as SX and sold at a discount. This way, Intel sold that which it would have otherwise thrown away.
How is this different? This is intentional. Intel knows that they can't beat AMD on performance, so they will flood the market with variations of the same chip. Intel is betting on the fact that Joe Q. Average will see how many 'different' processors Intel produces, and conclude that Intel is a better investment.
The performance penalty that Joe Q. Average will suffer by running a chip with a cache that is half the size for which most code is optimized is not really an issue for Intel.
Does anyone think that Intel bean-counters really care about the OPTIMALITY of the product? No, they care about it's PROFITABILITY. The stock-holders are the company's first priority.
As for the technical details.. CAVEAT EMPTOR, as always.
-- What you do today will cost you a day of your life.
Here's a HardwareCentral review of the Celeron 2 (today must be the day NDAs were lifted; look for other butt-kicking sites like Thresh's and Sharky's to maybe have something on it later today.
Here's BP6.com, an excellent reference for those of you with that funky Abit board. Check out the video preview of the Powerleap FC-PGA adapters - basically they plug into Coppermines and allow two of them (new stepping ONLY) to run in SMP mode. Of course, your BP6 would be running at 100MHz FSB by default - and overclocking well past 100MHz (which is what is required to unlock the true potential of Coppermines) is flaky on any BX board.
Coppermines seem, for me, an excellent buy. I have a 500E running at 733Mhz (147MHz FSB) on an MSI MS-6309 Apollo Pro 133A board. Excellent performance, and super stable.
The 66MHz FSB for these new Celerons is a double-edged sword. It's good that the 66MHz+ gap is open, which is really what made the original Celerons such good overclockers; but besides the performance hit (naturally), the lower FSB means a higher multiplier. The internal multiplier (locked by Intel) for the 600MHZ Celeron 2 is 9.0x. That's ass-high, people. I don't think many motherboards currently support that. At the very least I think a BIOS upgrade is in order, unless you're absoluely sure the board can handle that high a multiplier - but getting back to the performance hit, not only is your memory, etc. running at only 66MHz, but with the high multiplier your chip is running 9 times faster than your system. That's a low of waiting on its part.
My advice? Get a 500E or 550E (both can be had for around $200, if you know where to look) and overclock them beyond insanity. 150MHz FSB is not out of the question for these chips, especially the ones with the new core stepping. I'll be going for a 600E (FC-PGA) as soon as school lets out for me for the Summer.
For a truly bent journalistic look at the Coppermines, check out this piece I wrote for the fantastic Overclockers.com over Winter Break.
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Oscarfish.com: tropical fish with attitude. Way t
The trick to caching is that it speeds up repeated access to the same data or accessing data in nearby segments of memory.
When you are optimizing memory locations in your code (the OS or the applications), you optimize for vitual memory page sizes for memory usage, and for cache sizes to make sure that your application gets the most use of the cache as it can.
In a world where we get precompiled binaries (ideally you could teach the compiler to optimize for the different levels and compile it for different amounts, additionally programmers could put flags in their code for the different optimizations), how to we optimize our applications?
If the Celeron2 becomes really popular, then we optimize for 128K and 256K machines or 512K machines get little to know benefit from their larger caches. If we optimize on 256K or 512K, our smaller caches may get unacceptable cache miss rates and suffer poor performance.
The idea behind this is that 128K is aleady ~95% cache hit rate, and doubling the cache only gives small improvements. However, when Pentium Classic machines used to ship with 512K on the good boards and K6s and K6-2s were shipping on mobo with 1MB cache, why are we now switching down the amount for higher speed? I understand why it is faster (90% of L1 no slow down, 95% of L2 1 missed cycle; faster than 90% of L1 no slow down, 98% or 99% L2 of 3 or 4 missed cycles and memory access is 6-8 missed cycles)? Are our programs out there optimized for the older "larger" caches or the newer, "smaller" caches. It seems like we are going to see less and less advantage to the expensive systems with lots of cache when we are optimizing for the workstations with much less cache.
Alex
From where I'm sitting, Intel currently has an interesting problem. Their flagship processor line, the Pentium III Coppermine, tops out at 1GHz . But there aren't that many around, and the current crop of PIIICu's seem to top out at 800MHz. Overclockers can squeeze this up a bit, but it seems that the PIIICu's in the shop are close to their limits anyway. Celeron's have always proved to be seriously overclockable - most 500MHz will go to 600MHz plus, which leads me to believe that Intel is not being anything like as strict in the CPU speeds it's binning its processors into.
In other words, the Celeron processors are not being tested hard as they come off the production line as there is an adequate supply of the speeds that Intel wishes to see. Why doesn't Intel want it's Celerons to be sold as close to the limiting speeds as possible? In my opinion, it's because they don't want to eclipse their PIIICu flagship chips with Celeron chips running at the same clockspeed as this would dilute their market with their own product.
So what you cry? None of this would matter so much if AMD wasn't quietly pulling ahead in the high-speed chip fabrication stakes. With the Athlon coming off the production lines at clock speeds 850, 900, 950 and 1GHz, there is considerable pressure on the PIIICu's to remain visible in the marketplace, since they are the direct competitor to the Athlon. The Celeron 2 looks to be throttled by it's bus speed (66MHz?) in comparison to the Athlon at 200MHz, and won't compete in heavy memory fetching tasks, such as games, art programs, complex DTP etc. Until Intel can successfully ramp up the speeds on it's headline brand, the increasing speeds of the Celerons and Celeron 2's present an interesting dilemma.
Cheers,
Toby Haynes
Anything I post is strictly my own thoughts and doesn't necessarily have anything to do with the opinions of IBM.