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IBM Creates New Processor Production Method
Vandermar writes: "IBM's new production method uses an advanced insulation material -- a low-k dielectric -- that protects the millions of individual copper circuits on a chip." Apparently it works at sizes down to 0.13 micron and the insulation itself is primarily silk. IBM says it will be using this technology for its Power 4 processor, but with their technology sharing with Transmeta and AMD can we expect to see this enhancement in their chips?"
"...IBM has developed a proprietary technique to build chips using silk, a low-k dielectric material that is commercially available from the Dow Chemical Co. (DOW.N)."
Probably an acronym of SIlicon, Low-K.
The approaches I've read about to date mostly involve "foaming" whatever material is used, as vacuum or whatever gas ends up in the cavities doesn't have nearly as high a dielectric constant.
Parasitic capacitance is directly related to the dielectric constant of the insulating material.
I think a big question here is, does this impact Apple? With Motorola holding up the release of faster G4 processers, etc, and with IBM just coming up with blazing technology such as this, where does Apple fit in? Obviously, if Motorola had it's act together, this IBM announcement would be awesome news for Apple, but now, it doesn't do a whole lot of good for Mac users.
As you know, CPU's are damaged by electro-static migration, and heat
That's either electrostatic discharge (zapping the part) or electromigration (wiring atoms getting knocked out of place by speeding electrons). Please don't combine the two.
Actually, the low-K dielectrics make the electromigration worse, not better. EM effectively causes pressure inside the 'downstream' (positive) end of the wire, where aluminum atoms pile up and press against the surrounding dielectric. All of the proposed low-K dielectrics are physically weaker than silicon dioxide, and thus the EM limit is lower.
Lacking <sarcasm> tags,
One possible problem is poor heat conduction from die to package, but the tradeoff is probably worth it.
Non issue. IC dice mount with the back of the die, not the active side, to the substrate. Even flip-chip (solder-bump) parts have to use a thermal contact on the other side for all but the lowest power dissipations because the total contact area on the metalized side must be a small percentage of the total.
Lacking <sarcasm> tags,
Basicly delay is proportional to R*C - the resistance of the wire times the capacitance of it. You can reduce the resistance by using a more conductive metal (like Cu rather than the more traditional Al). You can reduce the capacitance by:
- reducing the wire's area (but 'edge effects' - proportional to the length of the wire don't scale in the same way as other features so this is becoming problematical)
- moving the wire further away from other wires (but we're trying to make things smaller to fit more stuff in, not bigger)
- use an insulator between the wires with a lower dieletric constant (what's happening here)
5 years ago we designers didn't care much about wire delays - they weren't what made our logic slow - now they're killing usPS: Intel's 'coppermine' processers don't use copper wires - marketting is everything ....
If the technique is proven viable, IBM will surely get their patents in a row and start licensing the technology to all comers. Just because they have tech sharing with Transmeta and AMD doesn't mean that Intel, Motorola and Via are not going to be able to get their hands on this. IBM's revenues are not solely from hardware sales, and certainly not from chip sales alone. It is in IBM's best interest to license the patents out to whomever will pay for them.
So, on that note, I do believe that Transmeta and AMD will end up with this technology, assuming it is useful.
From http://www.dow.com/dow_news/co rporate/20000403a.html:
The Dow Chemical Company is supplying IBM with SiLK* semiconductor dielectric resin
This is an artificial polymer with a low dielectric constant. Not the silk used for cloth.
The article also gives a moderately technical description of why a low-k dielectric is a Good Thing.
The industry's been working on low-k dielectrics
for a long time.
The real issue with low-k dielectrics is that they
reduce the capacitance of the onchip wiring.
This has several benefits:
1) Wiring capacitances in general will be
signficantly reduced.
2) Wires running parallel to each other will
have less crosstalk. I.e., if the voltage on
one wire switches, it'll have less tendency to
drag the voltage of wires close to it with it.
This is a result of neighboring wires having
mutual capacitance. --> EASIER DESIGN
3) Since capacitances are reduced, less power
will be needed to cause metal wires to switch
voltage. --> COOLER CPUs, -->LOWER POWER
4) Because of the reduced capacitances, it requires less current to switch wires.
--> FASTER CPUs.
This is a really significant advance by IBM,
maybe more signficant than copper metallization.
One possible problem is poor heat conduction
from die to package, but the tradeoff is probably
worth it.