Slashdot Mirror
Intel Releasing PIII Xeon Today
BMIComp writes "Yahoo! news is reporting that Intel is going to introduce their Pentium III Xeon Chip, today. " .18 microns, 700 Mhz, and integrated cache. The article talks quite a bit about how the new Xeons are going straight for Sun's throat.
I tried to post this with this news story. It's on C|NET. They both sat pretty much the same thing.
Devil Ducky
Devil Ducky
MY peers would get out of jury duty.
Remember the Celeron 300 and 300a? Case in point. The more the better. Your logic is flawed here. It's true that going from the cacheless 300 to the 128k cache 300a was a huge improvement I wouldn't say "the more the better." It depends entirely on what application you are using the proc for.
For instance, a computer with 32MB of ram is going to run a ton faster than one with 8mb of ram, but one with 1GB of ram isn't going to run that much faster than one with 256MB of ram for normal applications. Only really high-end apps need this much.
The Xeon is aimed at High-end servers which could probably benefit from the cache, but is the price worth it? I dunno.
The main reason to buy one, as you stated, is for the >2 SMP. AFAIK the only difference between the MP capabilities of the Xeon line and the regular line is that the PIII's are purposely crippled to only run on 2x SMP. It seems like a rip that Intel would do this and then charge an arm and a leg for almost the same proc with SMP turned on.
http://overwhelmed.org
Ushers will eat latecomers.
IP is just rude.
Is there any torture so subl
As far as I can tell, the most the Xeon can scale to is 8 processors.
And it doesn't do that well. Intel's 8 way chipset is crap. To grossly oversimplify it's two 4 way shared busses communicating over yet another shared bus. It performs about how you'd expect. Compaq has a better 8 way xeon chipset, but if they're not your hardware vendor, you're SOL.
Somewhere Scot McNeally is screaming "Help, I'm being menaced by a dwarf!"
Or not.
--Shoeboy
(former microserf)
What makes the Xeon better? The cache is larger, yes? Everyone else on Slashdot knocks L2 cache saying it's overrated and underutilized as is.
For most personal systems, adding cache would give diminishing returns fairly quickly. However, a personal system usually has one or at most two major tasks draining resources. A server has many cpu- and memory-intensive tasks running at once. A small cache would thrash on every context switch. A larger one wouldn't. Of course, how much of a performance gain this gives depends on how long the timeslice is, but if the timeslice is short enough, it's relevant.
Anyone have any insight as to what makes the Xeon a good choice in the server arena?
Probably price. A Xeon system is cheap compared to its competition, if I understand correctly. It doesn't scale as well as a Sun box, and won't give you the floating-point performance of an Alpha box, and doesn't have the memory integration of an SGI box, but as an inexpensive mediocre solution it can be a good buy if you don't really need something cutting-edge.
Besides being a patently dumb name (sounds like a new Noble gas), Xeon is a chip with split personalities.
The original PII Xeons were the standard Deschutes (.25 micron PII) cores with full-speed L2 cache at 512 KB, 1 MB, and 2 MB. Those were replaced by the PIII Xeons that had the Katmai (.25 micron PIII) core with the same cache and sporting the addition of SSE. Both were rated for up to 8-way SMP. These are the Xeons that maxed out at 550 MHz.
There are a newer batch of Xeons based on the Coppermine core (.18 micron) that don't really differ from today's PIII's except that they are rated for multiprocessing (2-way only, I think). The Coppermine Xeons have 256 KB of on-chip L2 cache, just like the Coppermine PIII's, and can run on the 100 MHz or 133 MHz GTL+ bus, just like the Coppermine PIII's.
Skip ahead to the last week. PIII's are now rated as SMP (2-way only) capable. The Xeons being announced have SSE and on-chip cache, but the cache is (mostly) the same size as the old Katmai Xeons, namely 1 MB and 2 MB. I guess 512 KB is gone for good. Also, the new high-speed Xeons are capable of 8-way SMP, like the old Katmai and Deschutes Xeons.
One interesting note on the stability and scalability of Intel's bus design (remember it's been in use for 5 years+) is that they have pushed a bus that started at 60 and 66 MHz to 133 MHz, but in order to allow SMP beyond 2-way they can't get above 100 MHz.
GK
Please note that I did this all from memory and with all the holes in my for eating and hearing and whatnot I'm surprised all my memory hasn't leaked out yet. Now warned, you may flame away.
Sun's architecture is based on high-speed switches connecting multiple fast/wide PCI or Sbus buses. The peecee architecture is based on having one to four PCI buses on another shared bus. Suns have memory buses no less than 1152 bits wide. Peecees generally have 256-bit memory buses. Summary: Suns can move far, far more bits around inside them than any peecee server can. Sun 4, Intel 0. It should be noted that this isn't entirely Intel's fault, but they aren't really helping anyone do something non-peeceeish. You _could_ build a Sun-like system with Xeons, but nobody does.
The peecee architecture is hopelessly obsolete. 16 bit bootstrap code. A BIOS. Forget boot monitors and intelligent peripherals, you know, things that make systems manageable and flexible (just try booting a peecee from tape - you can't - or over the network - that'll cost you extra). Both system architectures have their roots in the late 70s and early 80s. Sun started with a good design and have steadily improved and enhanced it. The peecee started with a poor design and have left it essentially unchanged for 20 years. Sun 5, Intel 0. Again, not all Intel's fault, but since there aren't really any other systems available using Intel CPUs, it counts against them anyway.
Now, even with these drawbacks, I could see the Xeons being a good choice for a midrange server if they cost much less than the Suns. Unfortunately, the Xeons are actually more expensive than the UltraSparcs, even at the same clock and with the same size L2 cache. If you have $4k to blow, you can get either a Xeon 500 w/2MB, or an UltraSparc 450 with 4MB. And the UltraSparc is faster, too. Oops, guess that's 3. Sun 6, Intel 0.
But it's not necessarily the truth.
The truth is that for a whole lot of the applications for which people are installing big UltraSPARC boxes, the applications are not CPU-bound, but rather I/O bound.
Having a better, faster Xeon Pentium III processor doesn't help with either of these things.
What helps with such applications are:
Which Seagate and Quantum and IBM are responsible for...
Think Adaptec, maybehaps?
Which means more than the 8GB that appears to be supported at this point.
If you're not part of the solution, you're part of the precipitate.
Keep in mind, Microsoft wants everyone to think DNS stands for "digital nervous system", too. Fuck that!
- A.P.
--
"One World, one Web, one Program" - Microsoft promotional ad
"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
The thing about CISC is that they have a habit of using microcode to translate all of the complex instructions into smaller ones for the core of the processor (AFAIK). The time it takes to decode instuctions is considerable at this stage, sith several hundred instuctions.
Trust me on this one - it's at most one clock, and possibly less. This goes for the x86 instruction set especially; each byte of the variable-length instruction has a fixed purpose, instead of being completely random. To process this, you need to prefetch several bytes ahead and have three or four shifters and a MUX to select and align the next instruction while you're processing the current one, giving a throughput of one instruction fetched and aligned per clock (or more, if you add more silicon). Once the instruction is aligned, you read out each of the fields that might possibly be there, and use a MUX to select them. You have a combinational logic block that processes the opcode and tells you if this is an instruction that can be processed atomically or that needs to be broken down, and a lookup table giving a series of RISCian stages for multi-clock instructions. If the "multi-clock" flag is set, you stall the instruction fetch unit and route in instructions from the lookup table instead.
It should be noted that processing the argument-location byte may insert memory load/store instructions too. However, as these are very predictable, you don't need a table lookup for them (just stalls and instrucion register preloads at appropriate times).
Lots of extra silicon, but little extra time. You do much the same thing in a RISC processor, except without the alignment stage or the lookup table.
As the article says, Pentium III Xeons have been around for a while, but were topped out at 550 Mhz. This is just faster (and different layout, I think).
I cannot give you a whole lot of technical detail, but practical data I have. I have a SuperMicro S6DGU dual Xeon board on which I run two 500-MHz 512k units. I have compared these to a similar SuperMicro dual P3 board, and did some time comparisons in both SCO UNIX and in WinNT 4. In both cases, the Xeon was between 10 and 25% faster at the same clock/processor speed depending on the application.
At the time, I did not test multiprocessors, but I can only suppose that the margin would widen due to better SMP support within the Xeon/GX chipset. Also notable is the difference in chipsets between the BX and GX I tested with. The GX may make my setup a little faster with memory interleaving, more efficient bus arbitration, etc.
What remains to be seen is whether the cost difference justifies the performance difference for small servers, workstations, and hobbyist users. Can anyone kick in their deep technical knowledge of these chips?
-L
Intel might claim that they are going for the throat with the PIII Xeon, but they have a huge gap to close before marketing catches up with reality.
...same as a standard PIII.
As far as I can tell, the most the Xeon can scale to is 8 processors. At least that is the largest machine I can find for Xeon. Sun's midrange machines _start_ at 4 processors and, for now, go up to 64. The planned maximum for UltraSparc III is 1024. Sun 1, Intel 0.
UltraSparc is 64 bit, Xeon is 32.
Sun 2, Intel 0
UltraSparcs have had integrated caches for quite a while, as far back as SuperSparc I. On the current cpus, the desktop boxes can have up 2MB cache, the midrange servers 4MB, and the large Enterprise servers get 8MB cache. The PIII Xeon's claim to fame is the extra electronics they add to the processor card which allows some hardware admin of the processor. The cache size is 256KB
Sun 3, Intel 0.
Until Intel produces a cpu which can scale well and has an OS which supports that scaling, I don't think Sun has much to worry about.
And for those of you who think MHz is a consideration, bzzzt! In the world of 24x7 server farms, torque counts more than horsepower. The UltraSparc cpu can handle a much greater load without sweat than most other cpus. The UltraSparc was designed to handle massive loads. So, while the UltraSparc will likely lag behind an equivalently rated Intel cpu, which would you rather use to make a cross country houshold move: A Kenworth or a few dozen pick-up trucks?
In the immortal words of Socrates, who said; 'I drank what?'