IBM Announces New AS/400s With SOI Chips

Chris Brewer writes: "IBM announced today a new line of AS/400e servers powered by the world's first production chips made of silicon-on-insulator (SOI) transistors and copper wiring. They say the addition of SOI adds a further 20-30% to performance beyond copper. They have a new high-end server that's 3.6x faster than before, entry level servers for running Domino (and presumably Linux), and all support XML. Further details can be found at IBM's AS/400 site. "

Comments

Re:Fast chips and XML?

[Vanders]

Suer, i await the time when all press releases simply say "New hardware, faster, more expensive, fancy new production process. Linux, XML, WAP, Internet, WWW, Open Source, multimedia, next generation. You want one."

It's sure to be a winner, it's got all the buzzwords.

Re:Brief guide to SOI

[stripes]

RCA had silicon on sapphire for the 1802 microprocessor back in the early 1980's. One of the benefits, as I recall, was radiation resistance (works great in satellites).

Yep, five+ years ago you could get a silicon on sapphire MIPS R3000 (or R2000? I think R3000), it ran at 25Mhz I think, and cost over $10k.

I think IBM's contribution (this time around) to SOI is that they have a way to do it without incresing costs dramatically.

However I'm not a process expert, so take this info with a grain of sand. Sorry.

Re:Brief guide to SOI

[Alan G]

Why SOI?
The gate of a MOS transistor is essentially a capacitor, and the speed at which it can operate is determined by how long this capacitor takes to charge/discharge.
Basic physics will tell you that the thicker the capacitor, the smaller its value, and the faster the transistor. By putting the transitor on an SOI wafer, the silicon-dioxide layer acts as extra thickness for the capacitor, reducing its value, and making the thing faster.

Erm, not exactly.

You're right that gate capacitance is important, but what's really affected by the insulator layer are two different things:

• junction capacitance - This is the capacitance of the source and drain, and it's formed by the parasitic PN juntion at the boundary between the source/drain and the bulk silicon. It includes both a sidewall component (formed by the vertical boundary between the source/drain and the bulk) and an area component (formed by the horizontal s/d-bulk boundary at the bottom of the source/drain). This latter component is eliminated in SOI, because there's no bulk silicon under the device.
• body effect - A posistive voltage difference between the source and the bulk causes the effective threshold voltage to rise, which means the transistor is harder to turn on. Since there isn't any bulk below the channel, there isn't a mechanism for the bulk bias to affect the threshold voltage. This is especially important when you have stacks of transistors, e.g. in the pulldown path of a NAND gate.

There's more on this at IBM's web site.

SOI chips?

[seldolivaw]

Are they anything like those awful soi burgers?

Ugh. They'll never catch on.

Brief guide to SOI

[TonyJohn]

For once I can be informative, so I will.

SOI = Silicon-on-Insulator
Most chips are fabricated on pure silicon wafers. SOI wafers have a layer of silicon dioxide close to the surface. The transistors are built above this layer.

Why SOI?
The gate of a MOS transistor is essentially a capacitor, and the speed at which it can operate is determined by how long this capacitor takes to charge/discharge.
Basic physics will tell you that the thicker the capacitor, the smaller its value, and the faster the transistor.
By putting the transitor on an SOI wafer, the silicon-dioxide layer acts as extra thickness for the capacitor, reducing its value, and making the thing faster.

TJ

XML

[captaineo]

...and all support XML

Whew, for a second there I thought IBM was trying to push a non-XML-compliant processor. Could have really hindered its adoption in enterprise computing.