Moore's Law set to continue

Chips are made by etching tiny wires and transistors onto a silicon substrate. The process used is lithography, which resembles photography: layers of special chemicals are added onto the silicon base. Shining light through a mask changes the properties of the layers where the light hits, allowing further treatment to produce transistors, wires, and other so-called features. Classical physics limits the size of features achievable with a given wave-length lambda to the Rayleigh diffraction limit of lambda/2. This is achieved by using optical interference. In 1999, Yablonovitch and Vrijen suggested using two-photon exposure techniques to increase this resolution. Their interference pattern contained a high frequency 4* term (allowing lambda/4 sized features), but also a lower frequency 2* term of greater intensity which made it unusable for lithography. Now researchers at the JPL (USA) and the University of Wales (UK) have shown that using entangled photons removes the 2* term allowing features of lambda/4 to be created. Their paper goes on to show that in general features as small as lambda/2N should be possible for N-photon absorbing substrates. Slashdot contacted one of the authors Jonathan Dowling who told us that experimental validation of these results is underway at UMD and is looking good. This means that Moore's law that the speed of chips will increase two-fold every 18 months will probably not encounter a limit due to lithography. Thanks to B1FFMaN for bringing the story to our attention, and to Jonathan Dowling for emailing us the article in advance of its publication.

Comments

what about interconnect, leakage, and power diss.?

[crgrace]

While photolithography certainly is one of the potential limits to Moore's law, it is not the only one, nor is it the most difficult. For years we have had electron-beam lithography but it is expensive, and that is why we have pushed optical lithography to such dizzying heights. There is no technical reason not to use E-beam lithography, but there are economic reasons.

But consider:

1. interconnect: as feature sizes diminish, the physical height of metal lines becomes greater than their width, making them look like skyscrapers, and the IC isn't so planar anymore. The problem then becomes the physical strength of the conductor, as it easily breaks as it is forced to bend over the surface of the chip. Copper interconnect is one partial solution to this problem, but it is not a magic bullet and things are getting worse all the time.

2. leakage: as transistors shrink, their gate oxide also scales. Therefore, for a given supply voltage, the electric field in the transistor increases until the gate blows out. So, then power supply voltages are scaled. Unfortunately, this tends to slow down the transistor unless the threshold voltage is also reduced, but then we have increased leakage current. This is quite a trade off, as increased leakage current not only increases the power dissipation (more on this next) but it also makes it more difficult to design RAM and mixed-signal/analog blocks.

3. Power Dissipation: Even though the supply voltage is decreased, and power dissipation of a single transistor decreases as the square of the supply voltage, overall power will increase for two reasons. First, there are many more transistors on the chip switching ever faster, and second, the reduced threshold voltages mean there will be significant static power drain even in CMOS logic. 1 nA of leakage/transistor in a 1 Volt, 1 Billion Transistor microprocessor of the future would burn a full Watt even without switching! This is a very serious problem not only for portable applications because it is difficult to package such a power hungry chip cheaply and efficiently.

While this is an interesting development to optical lithography, I don't think it will have much impact on Moore's law. In fact, I'm much more worried about the power issue and The Interconnect Problem.

A few optics comments

[skoda]

I'm not in the litho field, but I know a small bit about it, and here are a few more thoughts on the issues:

- classical imaging is limited by wavelength; the shorter the wavelength, the better the resolution. Lithography, fundamentally, is imaging a mask at a reduced size onto reactive material. So, the approach has been to decrease the wavelength, to get smaller feature sizes.

- as the wavelength and feature sizes decreases, optical interference effects became more of a concern. But they also learned to play cool tricks with the effects. Instead of using a conventional 'binary' mask (either opaque or transparent), they implemented phase masks. Certain areas, usually at corners, and line ends, had a different optical thickness, introducing a phase shift into part of the light, allowing interference, resulting in certain feature sizes to be reduced, approaching the lambda/2 limit.

- Other games they play, I think, involve the etching material itself. Because it does not react in a linear fashion, I think they have done things to modulate the image intensity more precisely, using the material reaction with the light to achieve feature sizes that are smaller than expected based on the image quality itself. That is, the material is used as a thresholding device. (I'm not sure if they actually do this, but I thought I've heard of it. Maybe not.)

- What's next? People have been declaring the death of "optical lithography" for years (decades?). Yet, the industry keeps finding ways to produce shorter wavelengths (in an industrial setting), and design/fabricate lens systems that can image at that wavelength. There have been predictions of x-ray and electron beam lithography, but 'optics' has so far held them off.

What about this new technique? I don't know anything about it. It could be a new necessary method. Or it might not pan out, faced with the multitude of other challenges, and the tremendous money & experience & effort thrown behind the current optical technologies.

- Parting thoughts:
Something often overlooked are the other parts of lithograhy. The stepper motors used to translate the silicon wafers are incredible! But that technology must be improved to provide sufficient resolution & accuracy as feature sizes decrease.

The masks themselves are also a fair feat, requiring some fabrication finesse

The lens systems required for lithography systems are insane. The search for new materials as wavelength decreases. Further, as the feature sizes decrease, lenses must have ever small tolerances, which pushes the measurement technology people to do amazing things.

I could go on, but I've rambled enough. Suffice to say that the lithography and related fields are really cool. The particular writing method is important, but there are a whole host of other challenges to face as well.
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D. Fischer

Hard limit in lithography that is overlooked

[SysKoll]

I hate to rain on this parade of optimism, but there is a hard limit on the lithography process that everyone here seem to have overlooked.

This problem is the size of the photosensitive compound molecule. Whatever the wavelenght you use, you have to impress a photosensitive resin with your ever-finer optical patterns. And the problem is that this molecule is big. We are already reaching a point where the size of the photoresist molecule is not negligeable anymore.

In a few years, at around 0.02 microns, we'll reach the operational size of the smallest photoresist blob that can be physically impressed with a photon. So even if the wavalength keeps decreasing, we'll still have that blob size as the choke point.

Moreover, the new photoresists for 0.113-micrometer laser are far from being perfect. They are still way too temperamental for production use. And nobody has anything better coming up. None. No plans, no projects, no announcements.

Isn't that sad? For all the marvelous optical tricks that we pull in the micro-electronics industry, we are now roadblocked by a basic chemistry problem. Photoresist used to be a glorified paint job on top of a wafer that everyone was taking for granted, but it's back with a vengeance.

Conclusion: Unless we have a breakthrough in chemistry (not laser, not optics), the Moore law is dead when we reach 0.02 micron.

Re:what about tunneling?

[crgrace]

For computer chips this means that as the physical features on the chip get smaller and closer together, the electrons will be able to tunnel from one wire to another. This is called a tunneling current. As features approach 100nm it becomes fairly noticeable, and you have to start taking it into account.

I've never heard of electrons tunneling between wires. This would be a severe, perhaps fatal, form of crosstalk, and even in a 0.1um technology, the wires aren't necessarily anywhere near that close together. What you do see, however, is something called induced gate current where a MOSFET with supposedly infinite input impedence exhibts a bias current into its gate. This is because the silicon-dioxide layer between the gate and the channel is so small electrons in the channel can tunnel through the gate oxide and escape out the gate lead. This tends to make the MOSFET look a little like a Bipolar Junction Transistors, which people have been dealing with forever. The main effect of this induced gate current is increased power dissipation.

What is interesting is that a similar induced gate current can occur when operating a MOSFET at very high frequencies. The problem here is that when the frequency gets too high the capacitance between the gate and the channel tends to short out and provide a conducting path through the gate terminal. This is observed (and taken into account) in CMOS wireless/RF circuits.

Re:Innovation

[Procyon101]

It's amazing that something as revolutionary as the single chip computer could come out of an engineer staring at thirteen separate schematics and saying, "Ok, but what about doing this with one chip?" And then being in the right circumstances to do it.

The single-chip CPU is arguably the most important development of late 20th century, and it's exponential improvement (Moore's Law) is what drives the information economy. So what happens when Moore's law runs out?

If current trends are projected forward, by 2020 a bit of memory will be a single electron transistor, traces will be one molecule wide, and the cost of the fabrication plant will be the GNP of the planet. The speed of light imposes practical limits on how large you can make a chip and how fast you can clock one. This is why we'll have GHz chips, but fundamental physical laws prevent THz chips.

More importantly, the physical limits that shut down THz electronic computers apply to _any_ classical computing architecture; optical computing and other exotic technology can't beat the speed of light, or single-particle storage problems.

You can't win by going to SMP, because at best you get a linear increase with each processor; exponential increases in power require exponential increases in processor number, which require exponential increases in space and power consumption.

The only basis in physics for continuing Moore's law past classical computing is quantum computing. In a quantum computer N quantum bits (qbits) equals 2^N classical bits. This allows you to build a computer which scales exponentially with the physical resources of the computer. Quantum computing isn't a solved problem, but if and when it is it will be a revolution as big as the first single-chip CPU.