Moore's Law set to continue

Chips are made by etching tiny wires and transistors onto a silicon substrate. The process used is lithography, which resembles photography: layers of special chemicals are added onto the silicon base. Shining light through a mask changes the properties of the layers where the light hits, allowing further treatment to produce transistors, wires, and other so-called features. Classical physics limits the size of features achievable with a given wave-length lambda to the Rayleigh diffraction limit of lambda/2. This is achieved by using optical interference. In 1999, Yablonovitch and Vrijen suggested using two-photon exposure techniques to increase this resolution. Their interference pattern contained a high frequency 4* term (allowing lambda/4 sized features), but also a lower frequency 2* term of greater intensity which made it unusable for lithography. Now researchers at the JPL (USA) and the University of Wales (UK) have shown that using entangled photons removes the 2* term allowing features of lambda/4 to be created. Their paper goes on to show that in general features as small as lambda/2N should be possible for N-photon absorbing substrates. Slashdot contacted one of the authors Jonathan Dowling who told us that experimental validation of these results is underway at UMD and is looking good. This means that Moore's law that the speed of chips will increase two-fold every 18 months will probably not encounter a limit due to lithography. Thanks to B1FFMaN for bringing the story to our attention, and to Jonathan Dowling for emailing us the article in advance of its publication.

Comments

what about interconnect, leakage, and power diss.?

[crgrace]

While photolithography certainly is one of the potential limits to Moore's law, it is not the only one, nor is it the most difficult. For years we have had electron-beam lithography but it is expensive, and that is why we have pushed optical lithography to such dizzying heights. There is no technical reason not to use E-beam lithography, but there are economic reasons.

But consider:

1. interconnect: as feature sizes diminish, the physical height of metal lines becomes greater than their width, making them look like skyscrapers, and the IC isn't so planar anymore. The problem then becomes the physical strength of the conductor, as it easily breaks as it is forced to bend over the surface of the chip. Copper interconnect is one partial solution to this problem, but it is not a magic bullet and things are getting worse all the time.

2. leakage: as transistors shrink, their gate oxide also scales. Therefore, for a given supply voltage, the electric field in the transistor increases until the gate blows out. So, then power supply voltages are scaled. Unfortunately, this tends to slow down the transistor unless the threshold voltage is also reduced, but then we have increased leakage current. This is quite a trade off, as increased leakage current not only increases the power dissipation (more on this next) but it also makes it more difficult to design RAM and mixed-signal/analog blocks.

3. Power Dissipation: Even though the supply voltage is decreased, and power dissipation of a single transistor decreases as the square of the supply voltage, overall power will increase for two reasons. First, there are many more transistors on the chip switching ever faster, and second, the reduced threshold voltages mean there will be significant static power drain even in CMOS logic. 1 nA of leakage/transistor in a 1 Volt, 1 Billion Transistor microprocessor of the future would burn a full Watt even without switching! This is a very serious problem not only for portable applications because it is difficult to package such a power hungry chip cheaply and efficiently.

While this is an interesting development to optical lithography, I don't think it will have much impact on Moore's law. In fact, I'm much more worried about the power issue and The Interconnect Problem.