10GHz Processors And Moore's Law

AntiFreeze writes "There is an interesting story on MSNBC about Intel's attempts at producing chips capable of running at faster than 10 gigahertz. There was a previous /. article in early December about this here. This article from MSNBC is much more detailed (both technically and non) than the original article referenced from December, and provides a very intriguing look at what Intel's planning to do over the next four years, and what they'll have to show the general public as soon as April 1st. And as always, there's the heated /. argument about Moore's law buried in there, too."

Comments

Re:Dunno (Beowulf not the solution)

[Ouroboro]

Better off with multiple slower CPUs, like 1.5 GHz and Beowulf them. More machines to take care of, but better than rushed/poor fabbing of CPUs. Plus you get redundancy and almost unlimited scalability. And ungodly bandwidth if you use gigabit cards instead of just 100bt. It's the way to go for pretty much everything unless you have something custom for one cpu (which is rare these days)

Actually if you are going to have a system of highly interconnected cpu's like in a beowulf cluster then you are limited fairly severly in scalability. This is mostly due to the size of the memory bus. Even if you move up to gigabit ethernet cards the bus is a big limiting factor.

Secondly the class of tasks that a cluster is useful for is not that big. It does nothing towards making a really bloated program run any faster. They are not very good for real time tasks because once you have chopped up a problem and distributed it to all of the processors you have very little time to work on it and get the results back in time.

While very useful the cluster is not likely to be the solution to potential end of Moore's law like growth.

the end of software?

[maraist]

Ok, so what happens when we hit a practical mile-stone? Will faster general purpose CPU's achieve such a limit that it costs 10 times as much to achieve 10% performance gain?

Here are the alternatives. Get away from pipelining (which is a hack that facilitates ever-increasing clock-speeds).. Return to optimized and specialized adders / multiplers, etc. Now that we make things in parallel with 2 - 4 adders, simply produce CPU's with 24 adders, each with no inter-vening pipeline buffers.. The number of transistors significantly goes down for each adder, and through the use high conductive materials (such as diamond) you can achieve large surface area chips. (This assumes that you take on the reverse of existing P4's.. You have the control log and memory interfaces running at 10GHZ while your adder runs at say 100MHZ, which each gate switching with nearly 1/20GHZ probagation delay)

Step two is even more obvious. Specialized hardware.. In the video world, we have only to compare software OpenGL to hardware OpenGL. specialized hardware is monumental because it's the ultimate parallel algorithm. Those algorithms such as MFC, or possibly even OS calls could be hardware controlled.. Granted it makes upgrades a lot harder, but don't we find ourselves spending the money on new video cards every year and a half now? How often does someone upgrade winNT? It already costs $150 for the OS upgrade, what's an additional $50 for the PCI / adaptive AGP card?

To facilitate smoother transitions, I think that FPGA or ASICS might have a popularity explosion. As far as I know, they're still manufactured with huge gate-widths.. Bring an ASICs into the "10GHZ" range, and you have the potential for incredible performance.

In fact, the CPU as we know it might fade away into the anals of history over time. A return to cartraiges perhaps?

-Michael

Errm.....

[Ricky Cousins]

They'll have something to show on April 1st? Am I the only one who raised an eyebrow at this bit?

FIRST IMAGES BY APRIL

[myosin]

"We expect to have the first full field-scanned images by April 1," said Chuck Gwyn, program director for EUV.
Wouldn't happen to look like this would it? ;)


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"Almost isn't good enough - but it's almost good enough."

They made me make this point!

[phaze3000]

Does anyone else object to the way the article speaks about Moores law in an overly matter-of-fact manner, implying that it is just as much a law of Physics as Boyle's Law? A more careful journalist, rather than writing:

Moores Law, formulated by Intel co-founder Gordon Moore, states that the number of transistors a chip can hold will double every 18 to 24 months, as transistor size shrinks.

A more careful journalist would hopefully have written:

Moores Law, formulated by Intel co-founder Gordon Moore, speculates that the number of transistors a chip can hold will double every 18 to 24 months, as transistor size shrinks.

--

line widths

[Veteran]

Several interesting effects occur as line widths decrease. The first is that the working voltage has to go down: at .1 micrometer a one volt difference between the two sides of the line gives and electric field of 10 million volts per meter - which begins to approach the insulation capability of the best known insulator. In other words the insulators start to arc through. The cell wall of a neuron is so thin that the neuron is restricted to voltages of about 90 millivolts by this effect. The electric field problem is why present day processors operate at the approximately the 2 volt level.

Lowering the voltage has some good effects - the main one is that the power consumption drops as the square of the voltage (assuming Ohms law). However lowering the voltage causes everything to run slower. The old fashioned 4000 series CMOS chips were much faster at 15 volts than they were at 5 volts.

Chips get faster when they shrink because the capacitances decrease as the surface area of a conductor shrinks; cut the feature size by a factor of two in both directions and the capacitance is down by a factor of four. However there is another effect which occurs as everything shrinks; the insulation between features shrinks, and that shrinking feature increases the parasitic capacitance between the two features.

In the past the increase in capacitance caused by the thinning of insulators has not been a significant effect in limiting clock speeds but there comes a point where the effect does become important. In neurons the cell walls are so thin that the capacitance effects of the thin dielectric limit signal propagation speeds in the neuron to about 180 miles per hour or so. Long axons have thick sheaths to cut the capacitance and increase the signal propagation speeds.

This increasing capacitance with the decreasing dielectric thickness combined with the decreasing speed from the lowered voltages will eventually put an effective cap on the clock speed of silicon devices. The only big trick left in the book is too switch to Diamond based semi conductors - which are as much better than silicon than silicon was than germanium - and that will give us some more speed. Above a certain frequency Nature itself changes the way it does things. At RF frequencies bulk devices like crystals function - at the frequencies of light waves only atomic devices can switch from one state to another quickly enough.

In other words at some point in the near future we are going to reach a point where simple die shrinking won't be enough to crank up clock speeds any more. Enjoy things while they last - but another factor of a thousand increase in clock speed (Apple II one megahertz to present day one gigahertz) is going to be very difficult to achieve.