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PCI 3.0 Coming; Intel gets the Green Light.
pjbass writes "This story on ZDnet discusses the next I/O subsystem planned for PC's. It will be PCI 3.0 once making it to the consumers, but it is now known as Arapahoe, or 3GIO. Intel Corp. is responsible for making the technology, and boast its performance will be about 6 times that of PCI2.x, getting up to speeds of 6.6 gigabytes per second of bandwidth initially, with promises to scale more once the technology is mainstream."
AMD also voted for this too so we'll expect support for future Athlons (or more likely the Hammer). In the meantime Hypertransport is here for us to enjoy
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Actually, it is possible... Ever hear of multifunction cards? (i.e. quad ethernet) Then again, they probably just use their own PCI bridge chips to give them more bus...
Not to quibble, but while this might have been true a long time ago, it's certainly not true today. In a Sun Fire 6800 you can't write from memory to PCI space at more than 150 MB/sec, which is really terrible for a 64/66 PCI bus. (The PCI to memory speed in that same machine is about 370 MB/sec.)
Supposedly their next PCI controller chip will fix this problem, but that's what they said about the last one...
The last update I heard, was that AMD already had a new PCI bus (I thought it was PCI 2.0??), and the FCC was waiting on Intel. Because Intel was getting all upset that AMD had already made the standard and they weren't going to get their $$$. This was about 3 months ago, and I don't recall were I read it or I'd post it. I know the numbers are still the same (speed wise anyways), but what happened to AMD's new PCI? Did they even have one in the first place?
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You need to remember that AGP is PCI!
The AGP standard was derived from the PCI bus, but AGP is a port meaning only 1 device is hooked to the controller.
There may be a new AGP spec based on PCI 3.0, or due to it's point-to-point nature, it may not be even necessary to have a special device interface just for graphics.
In response to other posts, AGP 4X maxes out at 1.1GB/s while PCI 3.0 is initially proposed to go to 6.6GB/s and will go higher than that once the technology matures.
All in all this new spec is a Good Thing (tm)
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Oh great a new architecture. How long will it take before we get PCI 3.0 2x, 4x and 8x ?
Still waiting for that fibre-optic bus. Still waiting.
Weevil
ghaa.
If PCI 3.0 is going to be so much faster, what effect will that have on AGP. Will I have to go but a PCI videocard when I upgrade, or can I keep my AGP one?
I agree that motherboards will have fewer lines and thus be simpler because of the serialization of parallel lines. However, the serialization means that higher frequencies will be required for one wire to do what many parallel wires had done before. The result when moving to higher and higher frequencies is more cross-talk on the lines that are left. A good example is Rambus. From what I hear, there are lots of difficult issues with the cross-talk on the narrow bus.
JOhn
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"The key message is that PCI software and device drivers do not have to change to be supported in the base level of Arapahoe," Tipley said. "As far as the actual link level, how electrons get across the wires, that's quite different, and obviously won't be the same PCI pins. It will be very similar to what a link would look like for 10 Gigabit Ethernet or InfiniBand, that kind of signaling."
One Good Thing that the article failed to mention is that fewer wires also means it is easier to design a motherboard, and expansion cards, thus lowering the overall prices of both items (once the required chipsets get into mass-production, of course). You should also be able to get more spacing between the circuit paths, which should lead to a lower possiblity of cross-talk, and better reliability.
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I remember when I was a kid, seeing some article on Usenet circa 1990 about how it was impossible for any computer to do 30 FPS in 24-bit
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Hypertransport is a variable width, bi-directional bus. It can transfer up to 12GB/s. It can be used for many things - CPU - Northbridge (as it will be used for the upcoming Hammer CPUs), Northbridge - SOuthbridge, Northbridge - RAM, GPU - RAM, Southbridge - RAID controller, etc.
Hypertransport is packeted. EV6 isn't. AMD license EV6 from Alpha, AMD designed Hypertransport.
Is this enough to convince you that EV6 and Hypertransport are different?
ah, but do you have to explain to them the difference between pci 2.0 and pci 2.1 expansion cards? oh, what's that you say? you don't? oh, great.
that's because pci 2.1 compatible motherboards have been rolling out ever since that spec was finalized. and after that pci 2.1 cards were pushed to retailers. backwards comaptible, and transparent to most users.
next time you buy a pci card, check out if it requires pci 2.0 or 2.1. it'll be in the manual. and then you'll realize you've been able to match up yuor motherboard and your pci cards with little to no effort already.
complex
So will the connector be backwards-compatible? Or will we return to the days of three different bus connectors? (I'm not counting AGP, since there's always just one of those).
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer