PCI 3.0 Coming; Intel gets the Green Light.

pjbass writes "This story on ZDnet discusses the next I/O subsystem planned for PC's. It will be PCI 3.0 once making it to the consumers, but it is now known as Arapahoe, or 3GIO. Intel Corp. is responsible for making the technology, and boast its performance will be about 6 times that of PCI2.x, getting up to speeds of 6.6 gigabytes per second of bandwidth initially, with promises to scale more once the technology is mainstream."

Comments

Re:Lowered MB Costs

[Milican]

I agree that motherboards will have fewer lines and thus be simpler because of the serialization of parallel lines. However, the serialization means that higher frequencies will be required for one wire to do what many parallel wires had done before. The result when moving to higher and higher frequencies is more cross-talk on the lines that are left. A good example is Rambus. From what I hear, there are lots of difficult issues with the cross-talk on the narrow bus.

JOhn

Re:But is it backwards compatible?

[DeeKayWon]

Software yes, Hardware no. At least that's what I get from this paragraph:

"The key message is that PCI software and device drivers do not have to change to be supported in the base level of Arapahoe," Tipley said. "As far as the actual link level, how electrons get across the wires, that's quite different, and obviously won't be the same PCI pins. It will be very similar to what a link would look like for 10 Gigabit Ethernet or InfiniBand, that kind of signaling."

Lowered MB Costs

[nate1138]

One Good Thing that the article failed to mention is that fewer wires also means it is easier to design a motherboard, and expansion cards, thus lowering the overall prices of both items (once the required chipsets get into mass-production, of course). You should also be able to get more spacing between the circuit paths, which should lead to a lower possiblity of cross-talk, and better reliability.

No they are not the same thing.

[hattig]

EV6 is a 64-bit wide point-to-point processor bus used to connect Athlons and Durons to compatible Northbridges. It was developed by Alpha, and it can scale up to 200MHz DDR (400MHz effective). It can currently transfer either 1600MB/s or 2100MB/s.

Hypertransport is a variable width, bi-directional bus. It can transfer up to 12GB/s. It can be used for many things - CPU - Northbridge (as it will be used for the upcoming Hammer CPUs), Northbridge - SOuthbridge, Northbridge - RAM, GPU - RAM, Southbridge - RAID controller, etc.

Hypertransport is packeted. EV6 isn't. AMD license EV6 from Alpha, AMD designed Hypertransport.

Is this enough to convince you that EV6 and Hypertransport are different?

Re:What about AGP

[Syllepsis]

Sure, if you get a board w backwards compatibility. It took forever for ISA slots to dissapear. I remember there were boards with 3 PCI, 3 ISA, and 1 VLB slot. The AGP-Pro will perhaps take the place of the VLB as the outdated quirky standard still supported.

I bet you will not want to keep it though. PCI3 would offer a shared 6.6 GB/s peak versus an AGP 4x peak of 1 GB/s. At that point, a GeForce 3 MX PCI3 with 128 MB DDR-333 will most likely run for under $40 online, if they are still bothering to sell them. Drool...

PCI 3.0 implies backwards-compatibility

[AFCArchvile]

So will the connector be backwards-compatible? Or will we return to the days of three different bus connectors? (I'm not counting AGP, since there's always just one of those).