New Photolithography Process
dragons_flight writes "Motorola has announced a new photolithography process capable of making chip features smaller than 100 nm, with the aim of eventually going as low as 13 nm. For reference, the current next-generation standard is 157 nm."
developing photolithography
More of the above
Process description
A summer photolithography project
Does anyone else find the phrase "current next-generation standard" strange? My parser's still balking at it.
Being able to make "features" as small as 13 um (and remember, "as small as" means this is a lower limit, and includes all sizes larger than this, up to Ringworld and beyond....) does not translate into working transistors at this size. You start getting into quantum tunnelling through the gate oxide because it is too thin, you start getting into a very high on resistance because the channel is too thin, the interconnects start to electro-migrate at 1 volt, etc.
Making small features is only a very small part of making a working chip.
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