Slashdot Mirror
Intel Promises A Cool Billion (Transistors)
NevDull writes: "CNN is reporting that Intel has announced new semiconductor packaging which will lead to CPUs with a billion transistors running at 20GHz within 6 years. Yummy!" The advance here is removing the balls of solder between the chip's packaging and the microprocessor core, which leaves room for more transistors (or a thinner package). Like it says, though, this is years away from your pocket Cray.
At the least, we have *Crays* on our desks...
Actually, what Moore's Law essentially says is that the number of transistors on a chip will double every 18 months. The speed somewhat follows, but we have seen that simple scaling of transistor size is not sufficient to increase the speed linearly.
Take AMD for example. AMD stays with basically the same microarchitecture as when they first crossed the 1 GHz boundary, over 18 months ago. What are they at, 1400 MHz? That's a 40% increase in the past ~18 mos. Hmm...
Then you look at Intel. Intel practically abandoned the P3 to work on the P4, knowing the P3 was a dead end due to critical paths when scaling up the speed. The reason being that there are some parts of the microarchitecture that simply don't scale linearly with the rest of the process, primarily the memory system. Intel realized that the GHz race will guarantee market share, and has effectively succeeded in maintaining "Moore's Law" in the speed realm by scaling from 1GHz to 2Ghz in the same 18 mos. Sure, but it requires a reimplementation to do it.
If you scale these rates over 6 years, Intel has, yes the 2^4=16x increase you are predicting. AMD on the other hand has but a 1.4^4=3.8x improvement over the next 6 years. End result, Intel would have the 32GHz machine, and AMD would have the 1.4GHz*3.8 = 5.32 GHz Athlon that they call the Athlon 30K which actually performs as well as a 7 GHz P4, (yet still heats the small city.)
This really sounds bad for AMD, not to mention their incredibly-shrinking market share.
Intel has more info on this (both pdf's):
This backgrounder (4 pages, 17kb) has a basic diagram showing the change.
This briefing (18 pages, 2466kb) is a presentation, but actually has some nice detail. It has some photographs of the devices, better diagrams, and a picture of a naked man in the shower (really!).
I'll summerize:
PGA packaging (as used in many big processors) is basically a ceramic or fiberglass carrier board with pins on one side, wires in the middle (like a small PC board), and some method to directly attach to the chip. The chip is usually connected to the board with small solder balls, like BGAs, but on a smaller scale. The balls provide some flexibility and loose tolerances, but since they are bigger than the wires they connect they require a fairly large pad on the chip. This technology is a way eliminate these balls, allowing for smaller pads, freeing up more area on the die.
But you should check out the pictures -- they describe it better than I do.
HIV Crosses Species Barrier... into Muppets
Kind of. If one of your spacing limitations is due to I/O, and the limitation on the I/O is due to the necessity of placing huge (relatively) gobs of solder between the output lines and the package pins, then removing the solder may allow you to space I/O lines closer together, giving you more die space for logic.
But, yes, merely removing the solder doesn't change anything as far as the photolithography, deposition, or etching steps are concerned, and photo will still be one of the primary limitations in feature size (which then dictates just how many transisters you can pack into a square centimeter).
Intel is merely expecting some reduced power consumption (and thus heat production), and that this is "step in our march toward making processors with 1 billion transistors" not that this will itself allow such.