Intel Promises A Cool Billion (Transistors)

NevDull writes: "CNN is reporting that Intel has announced new semiconductor packaging which will lead to CPUs with a billion transistors running at 20GHz within 6 years. Yummy!" The advance here is removing the balls of solder between the chip's packaging and the microprocessor core, which leaves room for more transistors (or a thinner package). Like it says, though, this is years away from your pocket Cray.

Comments

Weird prediction...

[Hagabard]

Why would any CPU manufacturer attempt to predict processor design & clock speed six years into the future? It will be 2007 before this statement can be tested for validity at which point processor design could have changed drastically. Perhaps I should phone Cleo and ask her what the bus speed of my motherboard will be in 2010?

Hagabard

sounds like fun

[Lxy]

Except that clock speed is becoming a useless benchmark. At what point do we realize that Intel's 20 Ghz machine and AMD's 12 Ghz machine have an unnoticable speed difference? If they were talking about a pocket cray as suggested, yes, I guess there is a use for it. They're not talking about supercomputing, they're talking about Pentium 4's!!! At 20 Ghz you'd have to slow the thing down to play Diablo!!

Intel's challenge for current & future IC pack

[Anonymous Coward]

I have to commend Intel for trying to tackle a problem that is daunting at best. But there are enough problems with existing IC packages that need to be taken care of between now and then. These include:

1. High-speed signal isolation - two wires switching at enormous speeds like 10GHz are going to have effects on other signals in the package. There's enough trouble with this on high-speed multi-gigabit-per-second interfaces and even Rambus' crap TODAY. With signals packed in so close, how are they going to manage this tomorrow when the current memory bus is already at 3.2Gb/s? At 10GHz+, how hungry will the processor be for memory bandwidth? It's a fight between lower-speed highly-parallel signaling for density and higher-speed low-density serial signaling for signal integrity. A smaller package isn't going to help this. A larger package, even with fewer layers, will only aggravate signal coupling.

2. Power delivery and consumption - on some packages, up to 30% of the total connections are for I/O and core power delivery. Making these smaller as Intel proposes will not help matter, considering that switching at 10GHz is going to make power consumption skyrocket. How do they expect to get the power to the chip? People have enough problems today trying to bump their processor voltages up when they attempt to overclock. This is only going to get exponentially more difficult.

3. Die attach and reliability - I know they want to have solderless connections to the package. This is good - currently alpha particles from solder will occasionally cause false switching in memory elements. But with lots of heat cycles from power cycling up and down and questionable assembly yields that are usually tolerant to less than 0.5% from raw die to package. We take for granted the fact that the die will stay attached to the package today. How they will get the reliability to that point is beyond me, even if they've made a "major" stride. How do they account for field failures or age-related failures in a test lab?

4. Substrate material - the package material itself is critical to thermal matching on the board as well as to signal integrity inside the package. At the speeds they propose will the current substrates be sufficient for reducing signal coupling? As usual, material science is again lagging behind the rest, and we need far more research into exotic materials to be able to get fast packages going.

So, to me I think there's going to have to be larger packages with advanced cooling. I'm not going to get too excited. I certainly don't think that Intel will be able to take this course alone. What I forsee happening is to have new committees set up specifically for packaging as there are for IC process technology today. It's too capital and research intensive to be able to get away from having to use committees.

here's an experiment

[Anonymous Coward]

go back to 1995. ask Intel when Merced(now Itanium) would be out. now ask them how fast it would be in late 2001. now understand that what they say about 6 years in the future isn't worth a flying fuck

Huh?

[TheSHAD0W]

"Removing the balls of solder between the chip's packaging and the microprocessor core"...

Well, sure, that'd give you lots more room for transistors... It'd also give you a lot more room for defects to creep in. This is functionally no different from expanding the die size to the point where the CPU size is the same. While it might be less expensive than cutting fewer chips per wafer, it does nothing to increase the reliability of the process.

I think this is more of a pricing advance, and you'll see this lowering the cost of existing processor layouts, since you can decrease the die size without affecting the CPU design. But CPU size increases will still result in lower yield.

We already do, and have for years

[Ars-Fartsica]

Your computer spends most of its time just waiting for you to do something. If you have purchased a PC in the last six months (Athlon or P4) you certainly have far more CPU capacity than your I/O merits.

As for "code bloat" - deal with it, you are getting something bacl. Look at the memeory consumption for KDE2 vs. blackbox. sure, you are using ten times the memory, but in return you are getting a great deal of functionality. Your computer is there to be used, not preserved. Why not fill up that RAM? Why not saturate that CPU?

Just like they promised P4's with big caches?

[cnelzie]

If I recall correctly the original specs for the P4 stated a much larger cache and higher FPU. Then Intel found out that they would have to sell them for some insane price, like 1200 bucks, to make any kind of profit.

So, what did they do?

They clipped the FPU down to practically nothing, cut down the cache. Broke the JIT functionality and made the chip only able to really churn out specially optimized C code with any kind of speed.

Sorry, but MANY companies still use and program in COBOL, FORTRAN and PASCAL. Before any of you claim those are "dead" languages, remember that these languages run programs that have been in use on mainframes, companies spent millions/billions on, for more than 20 years. COBOL recently had some WWW extensions started or discussed a year or two ago as well.

I honestly have to question Intel's future processor roadmaps and production products when they show off things that are really to pricey for them to mass produce. It would be awesome if Intel was able to release the P4 like the original specs were. I would have one right now. The only thing is they didn't and the chip just ramps up the megaherts, but doesn't really do all that much more.

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