Slashdot Mirror
Scientific American on 3-D Chips
m5shiv writes: "Scientific American is running a feature on 3-D Memory Chips. These devices look like they will significantly reduce the cost of PDA's and other handheld devices as well as replacing analog film.
By stacking devices vertically, density goes up considerably. The company,
Matrix Semiconductor, appears to have some very interesting investors such as Kodak, Sony
and Microsoft."
If you read the bottom of the article, you notice the author holds 14 patents for this new technology.
Some of the founders had much to do with the founding of a company named Rambus, Inc. as well. Here's hoping they've learned from the mistakes of their former company.
I registered my hate for Jon Katz
Matrix 3-D Memory is a field-programmable, archival medium. Cards with 3DM are write-once and the programming can happen all at once or in parts over time. Once on the card, the data is secure for generations and can be read repeatedly.
So it's merely a writable-CD-on-a-chip. Maybe they will develop a rewritable version someday :-)
Omnis basim vester nobis compete sunt.
Just for the non-article-reading record, the application towards "digital film" is only that they expect to make really really dense memory devices, so what this technology may replace is CF, not chemical/"analog" film, or even its digital equivalent, like CCD's.
-- Watch the REAL Jon Katz.
This technology looks interesting but there is definitely a good share of hype in both the SciAm article and the company's web site.
In particular, there is a suggestion that there are cost savings in part because the surface area of a "3d chip" is less than "1d chips" since 1d chips have more surface area there is a greater chance a defect will happen within that area. (Thus "small yield.") This is a spurious suggestion for the following reasons:
1. Each layer of the "3d" chip is subject to abnormality risk. (Thus real risk is LAYERS x AREA x RISK. For 1d chip AREA is bigger, but LAYERS = 1.)
2. The chip is mechanically "ground flat" after each layer to prepare for the next. I'm sure this works and I am also sure there a failure rate greater than zero for this operation.
3. Perfect alignment of the layers is required otherwise one of more parts of the "cube" will fail. They are working on fault tollerance issues right now, and they should.
Bottom line is that every bad chip drives up the final production cost. This is true for 1d and 3d. Seems like all the risks of 1d apply to 3d and now there are a few more. How will this be cheaper in the short run?
Let's not get into the heat issue that has not been resolved.
I hope they succeed, but the oversimplifications made trying to sell this thing bug me.
--- -- - -
Give me LIBERTY, or give me a check.
It's a different Thomas H. Lee -- take a look at his Stanford faculty page. You can tell it's a different guy because the one at MIT died at age 77, and this Tom Lee is in his late thirties.
they are sort of the same thing. you are talking about what is used all the time for rapid prototyping. SLA or stereo lithography. notice the word "lithography". :-)
..In that a laser is used to form the poly, and in your example a laser is used to 'crystalize" the shape. In their chips ultra-violet lasers and photoresist, then etch, is used to make the shapes.
in their form of 3D chips (lots of other ways to do this), they lay down layers of poly, then laser anneal to get bigger single crystal grains, then mask and etch just like conventional silicon. So it is sort of the same.
I think it is somewhat futile to try to combine them when they are already so similar and the outcome is already determined, and existing technologies exist. but it is an interesting parallel.
agreed, it's mostly 1-D.
:-)
the channels are so thin, and short that basically the electrons/holes just shoot across (short channel effects aside). the width is primarily used by logic designers to account for loading (like multiple lanes on the highway).
now, device people have to take all 3D into account, but they basically end up back in a 1D approximation that works.
As far as the process guy people are concerned it's all in 3D and your cube with little windows is how doping works now. One doesn't need little windows, the dopants are injected or diffused into it. The "windows" are then closed by reducing the temperature, or "activated" by annealing.
in this case it is just stacked 2D, there is lots of research in the area of stacked 2D, both for real-estate (some phones have stacked processor/mem chips in them now. they are just connected with traditional wafer bonds)
and some for performance (like Matrix Semi.)
"lattice of atoms completely ordered throughout the chip we've got to think outside the box, this guy's inside the box, "
: actually he IS outside the box he's trying to use little bits of single crystal Si and fit his devices inside each little piece. that is VERY difficult and requires insane processing technology and alignment. OR in his case, reduntant ckts and error checking.
crystals are grown in 3d. they jsut can't be grown ontop of other stuff, or even on itself very easily without getting massive dislocations, etc.
i hope this made sense.
-eric
This has been discussed for years, but not using poly, using selective epitaxial overgrowth and polish back to make SOI islands. It has been demostrated at the university level while I was still there. Groups had begun to investigate the advantages of having the third dimension available for circuits. I believe they quickly realized that the complexity was overwhelming with no CAD tools available to handle the concept.
That's what I first thought, until I read further into the article. This is NOT a stack of IC's. It's a process for growing more layers of transistors on the surface of one IC. Theoretically, it should cost less than stacked IC's, and may eventually cost less than a set of "2D" (that is, single transistor layer) chips to be soldered onto a board side by side. (A significant part of the cost of a typical memory IC is in attaching the leads for the outside world, covering it in epoxy, and placing it on a board.) However, the cost savings depend on the percentage of finished chips that pass test; if you've cut the raw cost by 50% but cut the yield by 75%, then the cost per working chip is higher. The article doesn't say anything about yields, but if they are actually shipping production quantities for digital cameras, they probably doing fairly well at solving the yield issues, and will do better soon...
A digital camera is one application where density may count more than price, and I don't see how the Matrix chips can be beat for density. In conventional IC's, most of the silicon is below the active areas and only provides mechanical support. Stack those IC's, and you have many layers of non-functional silicon. The Matrix chip has just one.
Stacked chips have limited vertical interconnects -- either you connect them only at the edges, or you drill holes through the chips (much bigger than other IC fixtures) and metal-plate those as vertical wires. The Matrix chips can have true 3D interconnects, at the size of other IC features. This may not mean much to a plain memory chip, but it could be very important to other applications...
There is a Swedish company (subsidiary of the Norwegian company Opticom and Intel) developing stackable "3D" memory based on polymer films: http://www.thinfilm.se.
Irvine Sensors puts multiple pieces of silicon in the same package. Matrix is talking about putting multiple layers of devices on the same piece of silicon. Big difference.