Slashdot Mirror
Scientific American on 3-D Chips
m5shiv writes: "Scientific American is running a feature on 3-D Memory Chips. These devices look like they will significantly reduce the cost of PDA's and other handheld devices as well as replacing analog film.
By stacking devices vertically, density goes up considerably. The company,
Matrix Semiconductor, appears to have some very interesting investors such as Kodak, Sony
and Microsoft."
If you read the bottom of the article, you notice the author holds 14 patents for this new technology.
Matrix 3-D Memory is a field-programmable, archival medium. Cards with 3DM are write-once and the programming can happen all at once or in parts over time. Once on the card, the data is secure for generations and can be read repeatedly.
So it's merely a writable-CD-on-a-chip. Maybe they will develop a rewritable version someday :-)
Omnis basim vester nobis compete sunt.
Just for the non-article-reading record, the application towards "digital film" is only that they expect to make really really dense memory devices, so what this technology may replace is CF, not chemical/"analog" film, or even its digital equivalent, like CCD's.
-- Watch the REAL Jon Katz.
This technology looks interesting but there is definitely a good share of hype in both the SciAm article and the company's web site.
In particular, there is a suggestion that there are cost savings in part because the surface area of a "3d chip" is less than "1d chips" since 1d chips have more surface area there is a greater chance a defect will happen within that area. (Thus "small yield.") This is a spurious suggestion for the following reasons:
1. Each layer of the "3d" chip is subject to abnormality risk. (Thus real risk is LAYERS x AREA x RISK. For 1d chip AREA is bigger, but LAYERS = 1.)
2. The chip is mechanically "ground flat" after each layer to prepare for the next. I'm sure this works and I am also sure there a failure rate greater than zero for this operation.
3. Perfect alignment of the layers is required otherwise one of more parts of the "cube" will fail. They are working on fault tollerance issues right now, and they should.
Bottom line is that every bad chip drives up the final production cost. This is true for 1d and 3d. Seems like all the risks of 1d apply to 3d and now there are a few more. How will this be cheaper in the short run?
Let's not get into the heat issue that has not been resolved.
I hope they succeed, but the oversimplifications made trying to sell this thing bug me.
--- -- - -
Give me LIBERTY, or give me a check.
That's what I first thought, until I read further into the article. This is NOT a stack of IC's. It's a process for growing more layers of transistors on the surface of one IC. Theoretically, it should cost less than stacked IC's, and may eventually cost less than a set of "2D" (that is, single transistor layer) chips to be soldered onto a board side by side. (A significant part of the cost of a typical memory IC is in attaching the leads for the outside world, covering it in epoxy, and placing it on a board.) However, the cost savings depend on the percentage of finished chips that pass test; if you've cut the raw cost by 50% but cut the yield by 75%, then the cost per working chip is higher. The article doesn't say anything about yields, but if they are actually shipping production quantities for digital cameras, they probably doing fairly well at solving the yield issues, and will do better soon...
A digital camera is one application where density may count more than price, and I don't see how the Matrix chips can be beat for density. In conventional IC's, most of the silicon is below the active areas and only provides mechanical support. Stack those IC's, and you have many layers of non-functional silicon. The Matrix chip has just one.
Stacked chips have limited vertical interconnects -- either you connect them only at the edges, or you drill holes through the chips (much bigger than other IC fixtures) and metal-plate those as vertical wires. The Matrix chips can have true 3D interconnects, at the size of other IC features. This may not mean much to a plain memory chip, but it could be very important to other applications...