Anyone Using JHDL for Programmable Logic?

gte910h asks: "I am an embedded developer who is learning how to program programmable logic devices (CPLD's and FPGA's). I have looked at VHDL and other Hardware Description Languages, but they seem so obtuse compared to C or Java. Has anyone tried any of the tools based off of general purpose programming languages, like JHDL. Do they work as well as VHDL and other HDL's? These would make things this type of development acessable to more people if they work well enough." Are packages similar to JHDL available for other languages?

Comments

HDL 'programming'

[motorsabbath]

One of the hardest things we all need to learn when starting out with HDL is that we're not programming - we're building hardware and arrays of gates. Having done a *lot* of C and applications programming before I started on VHDL and Verilog I can tell you it took a while to shake off the programmer in me and become a hardware developer. Applying general-purpose programming tactics to HDL too often makes too many gates and highly inefficient chip and logic layouts.

Both VHDL and Verilog have their strengths - you'll get used to them. Especially if you have to sit down and hand-tewak the resultant logic aftewards ... Verilog is easier to write, but VHDL is (seems) more typesafe and is easier to debug.

Some thoughts from a JHDL developer

[omnirealm]

I worked in the BYU Configurable Computer Lab (the lab that developed JHDL) for about a year and a half. I built the JHDLOutput and the Design Rule Checker (DRC) components of the system.

One semester, the EE department decided to use JHDL as the HDL for the logic design class (then it was EE320), and I was the teaching assistant that "specialized" in the actual tool (JHDL). Basically, JHDL was used as an introductory HDL for the students. The results were interesting.

In short, most of the class succeeded in building an LC2 processor entirely in JHDL, interfacing it with memory, and programming it (netlist, run through Xilinx backend tools, transfer bitstream) onto a Spartan chip. Most of the issues arose in the students struggling with object-oriented programming (creating a "Wire object" and a "2:1 Multiplexor object") and in the subtle details of how to interface circuit components with one another. A lot of students would get sections of their circuits ripped out by the Xilinx tools for failing to simply attach one component to another. The schematic viewer, waveform viewer, and other debugging tools proved effective in helping with the actual design.

Automated and dynamic simulation is easily performed in the simulator GUI and in testbenches. There is a Finite State Machine generator. There is parameratizable Floating Point arithmetic unit (its size depends on the number of wires you pass to it when you instantiate it; there are many more modules like this). Parameters can be assigned to the circuits in JHDL to, for example, instruct the Xilinx tools how to assign pins to top-level wires. Multiclock functionality exists. My DRC subsystem can dynamically instantiate circuits and run user-specified (and user-defined) checks on those circuits through a GUI. JHDL is fairly sophisticated, and it is an impressive tool given that it is mostly a student-developed application.

Before I left the lab (I had a very heavy classload), we were kicking around the idea of making JHDL Open Source. There are many legal issues we had to deal with... I'm not sure how it's looking now.

Chip design != Programming

[Theovon]

If you're still quibbling about which HDL language to use, you need a few more years of experience learning how to design chips. The language is 1% of what you have to learn. Two years ago, I, a software engineer, was asked to design a chip for my employer, not because I knew anything about chip design, but because I was the only one who knew what was needed in the design. You should see some of the crap I wrote back when I first started. It's taken me two years to unlearn programming and learn chip design. They're nothing alike. I know Verilog syntax and semantics better than the senior ASIC designer we hired a year ago. His code is messier than mine, and he avoids certain features of the language, but his code synthesizes more easily to meet constraints. He's a better designer. Many programmers love abstraction. I do. Design a C++ class that performs some library of tasks and then forget about the internals of the class and just use it at a higher level in a bigger system. LISP is a WONDERFUL language for writing code at a very high level. Depending on your needs and your personality, there is a plethora of programming languages that provide different levels of abstractibility (is that a word?) and power. You must forget about all of that in chip design. If you try to abstract yourself too far from the hardware, the synthesizer is going to give you garbage. Some tools like Synopsys Module Compiler do a lot of the work for you and you don't know EXACTLY how it's going to pipeline your design, but you know, for the most part, what kind of hardware you're going to get. If you don't, then you're in trouble. When I was in highschool and was learning C, one thing I did was compile lots of little things to assembler and look at the results. I wanted to know what I was getting from my code. Given what I learned, I was able to optimize my C code much better. Likewise, when I started learning Verilog, I synthesized lots of small designs and looked at the gate-level results to see what I was getting. There were a number of things I tried to synthesize that I knew the synthesizer would choke on (because I knew that the design was counter-intuitive from a hardware perspective), and I got lousy results, as expected. One interesting rule of thumb in software development is that smaller code is faster. Although it's not true all of the time, statistically, if I write a function to perform a task and my code is significantly smaller than my co-worker's verion, my code will run faster. Exactly the opposite is true with chip design. The more explicit you are about the hardware you want, the better the synthesizer will understand what you want and be able to give you a good result. Remember that you are smarter than the synthesizer. Of course, telling the synthesizer that you want an adder is a bit of an abstraction over telling what gates you want for an adder, but nevertheless, when you say "a I'm sure some more experienced chip designers will see inexperience in what I'm saying, but from some of the other comments I have read, I think many generally agree with me. The bottom line is that although some languages may be better for chip design than others, good chip design comes from a chip-design way of thinking, which is completely unlike software engineering. One tip comes to mine, BTW. Many chips are embedded in systems with a CPU that will be controlling it. Don't try to put too much into the hardware. A little software can save a lot of hardware without any loss of performance or functionality.