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Anyone Using JHDL for Programmable Logic?
gte910h asks: "I
am an embedded developer who is learning how to program programmable
logic devices (CPLD's and FPGA's). I have looked at VHDL and other
Hardware Description Languages, but they seem so obtuse compared to C
or Java. Has anyone tried any of the tools based off of general
purpose programming languages, like JHDL.
Do they work as well as VHDL and other HDL's? These would make things
this type of development acessable to more people if they work well
enough." Are packages similar to JHDL available for other
languages?
One of the hardest things we all need to learn when starting out with HDL is that we're not programming - we're building hardware and arrays of gates. Having done a *lot* of C and applications programming before I started on VHDL and Verilog I can tell you it took a while to shake off the programmer in me and become a hardware developer. Applying general-purpose programming tactics to HDL too often makes too many gates and highly inefficient chip and logic layouts.
... Verilog is easier to write, but VHDL is (seems) more typesafe and is easier to debug.
Both VHDL and Verilog have their strengths - you'll get used to them. Especially if you have to sit down and hand-tewak the resultant logic aftewards
The heat from below can burn your eyes out
I'm surprised you didn't mention Verilog -- it's an HDL that is (outside of military contracting) much more popular than VHDL. The "obtuse" syntax in VHDL you mention is based on Ada's syntax -- both were designed essentially by committee. Verilog, in contrast, is based on C's syntax (with some Pascal thrown in).
VHDL has a much richer syntactic set than Verilog; however, it's easy to lose track of some of the features, and most synthesis tools need to convert to Verilog for gate-level representation of the code eventually. Some companies (such as Altera, with AHDL) have created hybrid languages that add some of the features to VHDL to Verilog; Verilog 2000 (which does the same, but isn't as widely proven yet) is another option. Still, if you want a simpler HDL than VHDL, I'd recommend Verilog.
The languages derived more directly from C and Java (SystemC, for example) are even less tested; it's hard to tell what bugs or other shortcomings exist in the tools. C and Java were designed without concurrent structures, and this makes me suspect HDLs derived from them will actually be more awkward than VHDL or Verilog.
This just reminds me of the differences in thought between EE and CS...
HDL's in java or C? HEH... What's next? x86 assembler implemented in java? ( pun
Maybe you should take a look here http://philip.greenspun.com/humor/eecs-difference
Damn CS's
The very reason languages like VHDL are "obtuse" is because hardware isn't the most intuitive thing out there. In order to make good chips, you have to thoroughly think things through, not just whip out some POS java script. VHDL is a good tool and I think taking C++ or Java code and making a chip out of it would only produce an extremely inefficient piece of hardware.
~ now you know
In my experience, things tend to work better when you go with the standard, which I would say is VHDL.
Last year, I was in a FPGA-based hardware design class, and during the early course of our group's project, we thought that maybe we'd be better served by switching to something easier to use. Long story short, we wasted three weeks trying to learn the "simpler" method which nobody at our school used, while the other groups plowed through VHDL, which everyone at the the school used, and they ended up with a better result.
I'm not saying "Because its the most popular it must be the best," but user base realy is a major decision when trying to go a particular route.
Some men spend their entire lives trying to kill themselves for having been born. --Ross MacDonald
I did not mean C-like syntax..
I am aware of verilog and other hdl's with "c-like" syntax...
but the way he worded that question seemed to imply something very different
"I don't care if it runs fast, programming it is EASY"
Damn CS majors...
~ now you know
Let's try that again.
There is a reason that it looks "obtuse" to you. The language is built to describe parallel things, i.e. stuff occuring at the same time, and at a VERY low level. As others have mentioned, it's built for EE work not CS work.
If you want something that is more C like, then look at verilog. I picked up verilog in 4 days and was producing useful hardware descriptions. I maybe have one advantage over you though. I'd been using pal programming languages like ABEL for 10 years before I ever saw Verilog. You might say my head was already in the right space.
If you want a free verilog compiler that covers 95% of the languages capability check out www.icarus.com
Have you compiled your kernel today??
Xilinx (FPGA semiconductor ompany) has a tool in early beta which let's you write Java, in a normal software way, which is then translated to Verilog. It looks pretty cool, and is free to use at this point (beta). Check out: this link.
They seem to have gotten some fairly decent speed/area results.
I haven't used it myself, but some friends at university are using it for modelling both simple and complex logic. They seem happy about it - the learning curve is not as steep as 'real' HDL languages, so its ideal for teaching as well.
The problem, i understand, is synthesis (the process of making hardware out of your source files). JHDL seem to lack those, but things might have changed...
So remember to check out the synthesis tools before you commit to JHDL....
Well, there's SystemC, which gives you a C-like syntax to describe logic at a stratospheric level. I tried playing around with it a little bit and it seems like it would be great if you had to crank out very small blocks, running at very slow speeds, multiple times a day.
But, if you're doing any kind of sizable project (like designing parts of supercomputers, for instance) then you'll just have to bite the bullet and learn how to design logic. VHDL is a little screwy, but Verilog is a breeze to learn and use. Just like you can't fake being a programmer, you can't fake being a logic designer. Just learn the background, there's no way around it.
When in Rome...
I can't belive I haven't seen this before but if we need any evidence that java is being used for way to much crap this is it.
Also the only reason you would have problems in VHDL is if you didn't understand how it works. When I got started in it I found I had to forget all the programming I learned and move into describing my circuts instead of trying to program their behavior. You'll find this type of mindset works well with VHDL/ABEL/Verilog.
I actually enjoy VHDL. I found it extremely easy to use once I realized that I wasn't actually programming I was just drawing with words.
Granted I was doing fairly simple things, (junior level Computer Organization class), but VHDL didn't seem obtuse at all to me.
I'm an ASIC designer and the team I'm on just wrapped up another chip. We used Verilog, which in my experience, is simpler than VHDL for *synthesizable* code (more on that later).
For the whole chip we used nothing but if-else, case, the usual boolean operators (and, or, xor etc.) and shifters. That's pretty much all you need. Loops, multi-dimensional arrays etc. aren't needed AND the synthesis tools will often either reject them flat out or construct very strange logic from them.
In order to "get" VHDL, you need to pretty much abandon all your software habits. Think in terms of parallel operations, not serial ones. Also, draw timing diagrams! They can be a real life saver.
Our company bought a soft IP core from a third party about a year ago. We got the VHDL source and everything. We tried to synthesize it and the tools eventually did it...but it took 14 hours. So, a few of us took a look at the code. What we saw horrified us. It was written in VHDL, but it was written in an extremely "software" like manner. A week later, we had re-written most of the offending blocks. The result was that the design synthesized in 4 hours and was 20% smaller.
Hmmm...I had a point in there somewhere, but it seems to have turned into a long rambling story.
Remember, coding hardware in an HDL is, and will probably never be, the same as writing software!
While they never say it explicitly, the J in JHDL is for Java. Read the papers on their website and you will see! Probably either legal issues with Sun or the obvious embarassment of mentioning Java in hardware design circles prevents it.
The difficulty is that Java is a serial language for designing software to execute on a serial processor. HDL's target devices that are inherently parallel, and have the extra complexity and difficulty that comes with that. There is currently *no* compiler that can get good performance out of serial HDL's. It's a different programming paradigm; you might as well ask for LISP that looks and feels like C. Even if you match the syntax, you still have to change paradigms to get any useful work done.
The area this targets (I believe) is unified design, where hardware and software (such as it is) for embedded devices is specified in the same language. They want to go for reconfigurable computing, you know, the one where you can perform parallel 1-bit additions twenty thousand times faster than a P4. Thing is, targetting hardware, which is inherently parallel, you need a language that supports that parallelism. J[ava]HDL just won't work, period.
Even Slashdot wants to hide some things
For very large designs, it is incredibly important to have a very good synthesizer, because FPGAs just aren't that big, and because hardware bugs are harder to catch (not only are there software bugs in hardware, but you can have bugs based upon physical problems) and more catastrophic.
However, there are really only two companies that make very high quality synthesizers: Cadence and Synopsis. Having used both of their products, I have to say that they only design for two languages: VHDL and Verilog.
And I must say, I don't blame them. Trying to extend Java to create hardware is crazy; they have to do a workaround in order to create multiple inheritance, as well as justifying the use of functions to specify IO properties of certian wires.
Syntax is sort of irrelevant, both VHDL and Verilog don't make this blunder. A function should not determine the properties of a signal - it makes a lot more sense that the only thing that functions can do is change the value of said signal.
Also, someone might try to use Java primitives that simply confuse the issue. VHDL has very basic support for primitives, which is very tied to bit manipulation (as well it should be, since each bit represents a single wire). Java isn't nearly as good without adding some non-inuitive (in Java) functions to the mix.
VHDL is not very close to ADA, despite a few slight syntactic elements. Verilog is not C, despite the same. They are HDLs, well suited to their tasks.
One final point: those languages (Ada and C) make good starting points for other languages. ADA provides the necessary strictness to ensure hardware design is not sloppy - a necessity since sloppiness results in errors and most hardware errors are impossible to detect during runtime. C was designed to be a low-level language, and to interface well with low-level operations, making it particularly well suited to the design of low-level systems. What other language makes a better starting place for a new languages design than these two based upon these lingual goals?
Mod me down and I will become more powerful than you can possibly imagine!
I think verilog has been mentioned already so I'll skip that (it's just VHDL lite IMHO). VHDL is around for a reason - it's about the maximum level of abstraction that's reasonable. High level (>=C) are great, but they work because microprocessors are designed to work with abstact structures. Hardware is just designed to work (usually). Think about it this way - if you want to program in C, program a *computer*, if you want to design hardware, keep in mind that you're designing hardware and *not* programming a computer.
If I'm totally off-base, and you were actually complaining about VHDL's crappy syntax (ON CLOCK'EVENT et al),just learn it - it's not bad at all once you get down to it, and it does make sense after you've used it for a while. (I hated it too when I first started).
I worked in the BYU Configurable Computer Lab (the lab that developed JHDL) for about a year and a half. I built the JHDLOutput and the Design Rule Checker (DRC) components of the system.
One semester, the EE department decided to use JHDL as the HDL for the logic design class (then it was EE320), and I was the teaching assistant that "specialized" in the actual tool (JHDL). Basically, JHDL was used as an introductory HDL for the students. The results were interesting.
In short, most of the class succeeded in building an LC2 processor entirely in JHDL, interfacing it with memory, and programming it (netlist, run through Xilinx backend tools, transfer bitstream) onto a Spartan chip. Most of the issues arose in the students struggling with object-oriented programming (creating a "Wire object" and a "2:1 Multiplexor object") and in the subtle details of how to interface circuit components with one another. A lot of students would get sections of their circuits ripped out by the Xilinx tools for failing to simply attach one component to another. The schematic viewer, waveform viewer, and other debugging tools proved effective in helping with the actual design.
Automated and dynamic simulation is easily performed in the simulator GUI and in testbenches. There is a Finite State Machine generator. There is parameratizable Floating Point arithmetic unit (its size depends on the number of wires you pass to it when you instantiate it; there are many more modules like this). Parameters can be assigned to the circuits in JHDL to, for example, instruct the Xilinx tools how to assign pins to top-level wires. Multiclock functionality exists. My DRC subsystem can dynamically instantiate circuits and run user-specified (and user-defined) checks on those circuits through a GUI. JHDL is fairly sophisticated, and it is an impressive tool given that it is mostly a student-developed application.
Before I left the lab (I had a very heavy classload), we were kicking around the idea of making JHDL Open Source. There are many legal issues we had to deal with... I'm not sure how it's looking now.
An unjust law is no law at all. - St. Augustine
And keep in mind that there are various levels of abstraction that you can use for VHDL. If you're going do to the gate level it's going to take you some good time to learn it but your chips will save money because they are smaller/faster/more efficient. Even if you don't learn the most abstract parts of the lanugage, you can still program the gate logic using C-like logical operators (which saves you huge amounts of time compared to cad tools where you have to connect the gates manually.)
The moral of the story: Spending the time to learn VHDL will pay for itself. The big chip manufacturers like Xilinx control large market portions, and their tools are VHDL-centric.
Hello,
I am a programmer and digital hardware designer with 10 years experience in both areas.
I find that VHDL, while obtuse, is a terrific modeling language. There is a steep learning curve associated with it. Once you get the hang of it, it can do many things for behavioral modeling and RTL design of FPGA's and ASIC's.
It has been said that once you pick up VHDL, Verilog is easy to pick up afterwards.
It really depends on what you are trying to do. Are you trying to realize a design into an FPGA? For example, VHDL code is written differently when modeling behavior. When you're using VHDL to implement a real design for an FPGA, the coding style is different and many techniques you've learned in CS do not apply here. Good coding practice still applies such as well definied variable/signal names, proper data typing, generous use of white space, and verbose comments. However, that is where the similarities between C coding and VHDL coding end.
The real issue here with VHDL design to an FPGA are the tools. How well the tool that you've chosen (i.e. Synopsis Design Compiler or Synplicity's Synplify) reads in your VHDL, parse it, and create a gate level design using the low level building blocks available for a given FPGA/ASIC family.
Because of this, the code needs to be written in a specific way. To implement a counter, you would need to write a specific construct that the synthesizer recognizes.
But, that is just the beginning of your problems, there is no real good way to have a synthesizer infer that you want a ripple counter, compact counter, balanced, and so on. The only way to get exactly what you want is to define it gate by gate, what connections are connected to what. This provides for zero ambiguity how the design is to be implemented in an FPGA and you gain something such as performance or decreased utilization (there is a trade-off somewhere). In my experience, I find that synthesis tools try to find a happy middle.
The problem as I see it with the JHDL and other languages that try to supplant VHDL/Verilog is that they haven't matured. You will be hard pressed to find adequate tool support for those languages. Synopsis provides support for System C (if I recall correctly) but Synopsis products are horrendously expensive ($60K a year MAINTENANCE fee alone). Recently, EETimes reported that EDA companies are generally not happy with System C right now as its touted benefits don't seem to be happening.
Should you choose something other than VHDL/Verilog, your choice of platforms may be limited as well, such as using Solaris which are not cheap. It depends on your outfit, can they afford the cost and be on the bleeding edge or is it a shoestring outfit scraping to get by where it can (i.e. affordable FPGA tools on affordable platforms)?
There is the long term to consider. If you were to successfully develop a FPGA design utilizing JHDL for the first generation. What happens if support for JHDL disappears when the time comes to do a 2nd or 3rd generation of your design? The long term outlook for languages other than VHDL and Verilog are unclear.
Hope this adds some insight to your questions.
...but I think it will be quite a long time before you see people like Intel, IBM, Motorola, Nvidia, TI, et. al. using this. Spinning hardware is *expensive* and you have to absolutely know your design is correct. AFAIK that usually means a tool that has been tested, inspected and ripped apart many times over. So perhaps five to seven years down the pipe, we'll be designing hardware in Java. But...
...people are making good points that hardware is not software. Everything is happening at the same time and if you are thinking in a one stream of execution state of mind you are not thinking in the correct problem space. The virtual machine that is presented by most operating systems is simply nothing like hardware. Not to say its bad, its just different.
I agree, the currently available hardward description languages out there (nearly nothing but VHDL & Verilog) are sorely behind the curve. Unfortunately, you're not going to get the support of the big EDA vendors (Synopsys,Cadence,etc.) if you go with an academically developed language like the one you mentioned. There are new languages coming down the pipe, however. A new Verilog standard was approved last year, which makes a few steps in the right direction. Also, there has been a good bit of momentum behind some newer languages, such as Superlog from Co-Design Automation, which is still under NDA, but looks like it has promise. HDLs develop very slowly. Companies invest millions of dollars in EDA software that only support the big two languages, and nobody is willing to budge unless everybody moves at once (sounds familiar!)
I am an electrical engineer who does ASIC/FPGA design and DFT, and if there is one thing I can't emphasize enough, is that when using HDLs, think about the hardware implications and don't just write straight code like you would in a functional program.
I have seen numerous designs done by primarily FPGA designers which use the languages (esp VHDL) very liberally, which usually works fine for programmable devices where the compilers can make your code work as long as it fits and meets timing, but when you want to put that code into an ASIC, it's a nightmare (non-synchronous design, no thought about DFT). Just like when doing OO programming, you need to THINK about your design or objects first, then code it up in C++ or VHDL _last_. It's a "description" language. HDLs should be used to describe designs that have already been designed in your head or on paper. The synthesis tools can do very funny things with code that is even functionally correct but just syntactically awkward. Sometimes, you just have to write the HDL in a manner that gets you what you want from the synthesis tools. Sometimes, good code in = garbage out! Writing code in high level languages puts another layer of complexity into the problem.
We are currently investigating some of the new tools that are starting to pop up out there for high level hardware design. It appears to me that using high level languages makes the most sense when you want to do functional type designs, for instance, DSP chips. There it makes PERFECT sense: you describe your DSP functions and algorithms in C just like you would if implementing it purely in a software application, and the tools can translate that into a decent HDL description for a signal processing core. Other things which are more structural than functional, are better done in one of the HDL languages. But we'll see. Doing circuit design in high level languages like C and Java is a New Thing(tm) and so the performance of these tools yet on really large and complicated designs isn't well known yet.
But if you want to learn HDLs, I would recommend starting with Verilog. It's based on C and is syntactically much less complicated than VHDL. Verilog is also faster than VHDL when doing large simulations. And remember that Verilog/VHDL code always executes in PARALLEL, since you're describing blocks of hardware.
A tutorial on Verilog is made available from a CMU professor. I think that Verilog will be more than sufficiently C-like to ease me into the PLD world.
I am aware of the huge difference of what kinds of behavior you are programming when you are using programmable logic devices vs. microcontrollers. But just because I am looking at a different paradigm doesn't mean it wouldn't be nice if some of my skills would transfer. I want to gain proficiency in PLD's because of the fact they can implement functionality otherwise requiring complex circuits. This is useful and I can't currently use it in my designs without another engineer to do the PLD.
I was really curious about the accessibility of the language. Java-like syntax would make it easier to entice more people to try to learn this skill, as Java is familiar to many people in the environments in which I work. I would bet Verilog has gained many adopters b/c of its similarity to C, who would otherwise use schematic entry to program PLD's, or avoid the parts altogether
To function well in the climate and level of embedded development today, you have to be able to do both sides of the equation if you want to be at all independent. I have seen horrific program design choices by people formally trained in EE, and I have seen atrocious, laughable circuits from those formally trained in CS.
A software guy sees a fault in a product and says it is a hardware problem.A hardware guy sees a fault in a product and says it is a software problem. The real engineer fixes the damn problem and tells the other two to grow up and pull their heads' out of their asses.
Want to see every step I took to start my company? http://www.rowdylabs.com/blogs/pitchtothegods
>Verilog is easier to write, but VHDL is (seems) more typesafe and is easier to debug.
About a year back I began doing some work in Verilog, because it was common in the area. Next chance I got, I switched to VHDL. Both languages were learned from scratch. The C vs Pascal comparison for Verilog vs VHDL is rather apt. I found that mistakes in my Verilog design would lurk much later into the build process, whereas most mistakes in my VHDL design would show up much sooner. With conventional programming, the difference may not be that great, because compilation isn't that 'thick' a process. With hardware design its much worse, with several stages of synthesis, timing, and only after that do you get into place and route. Some of my Verilog mistakes didn't show up until place an route, where I never had a VHDL mistake make it past synthesis. These are even mistakes that make it through simulation. HDL can be subtle indeed, especially for a newbie.
To some extent this comes back to the old C vs Pascal debate. Unfortunately Pacal was crippled by the limited library and other factors of its definition, so the debate could never be truly intelligently done. There's a tremendous amount of "Real Programmers..." macho crap in the debate too, further reducing the intelligence level. (training wheels references, and all that.)
Today we gripe over and over about buffer overflows, and wonder why they keep happening. It comes down to this: The C language is perfectly happy to let it happen, so preventing buffer overflows is completely up to programmer diligence. While you can probably come up with a buffer overflow in Pascal descendents (Gotta include that 'descendents', since pure Pascal is *practically* useless, I agree.) it almost takes work. No doubt there would have been no end of griping about that max_length on the strings, but then that's pretty much what needs to be done by hand for C.
Ada currently carries the Pascal-descendent banner, and is still alive with a reasonably vital community. Oddly enough, the US DOD has largely abandoned it, thinking C/C++ leads to cheaper development. Much of the new Ada community appears to be European, by the way.
The insiders' view appears to be, "Yes, it's more of a pain to develop the code, and that takes longer. But you buy all that back and more when it comes to debug and maintenance."
The living have better things to do than to continue hating the dead.
If you're still quibbling about which HDL language to use, you need a few more years of experience learning how to design chips. The language is 1% of what you have to learn. Two years ago, I, a software engineer, was asked to design a chip for my employer, not because I knew anything about chip design, but because I was the only one who knew what was needed in the design. You should see some of the crap I wrote back when I first started. It's taken me two years to unlearn programming and learn chip design. They're nothing alike. I know Verilog syntax and semantics better than the senior ASIC designer we hired a year ago. His code is messier than mine, and he avoids certain features of the language, but his code synthesizes more easily to meet constraints. He's a better designer. Many programmers love abstraction. I do. Design a C++ class that performs some library of tasks and then forget about the internals of the class and just use it at a higher level in a bigger system. LISP is a WONDERFUL language for writing code at a very high level. Depending on your needs and your personality, there is a plethora of programming languages that provide different levels of abstractibility (is that a word?) and power. You must forget about all of that in chip design. If you try to abstract yourself too far from the hardware, the synthesizer is going to give you garbage. Some tools like Synopsys Module Compiler do a lot of the work for you and you don't know EXACTLY how it's going to pipeline your design, but you know, for the most part, what kind of hardware you're going to get. If you don't, then you're in trouble. When I was in highschool and was learning C, one thing I did was compile lots of little things to assembler and look at the results. I wanted to know what I was getting from my code. Given what I learned, I was able to optimize my C code much better. Likewise, when I started learning Verilog, I synthesized lots of small designs and looked at the gate-level results to see what I was getting. There were a number of things I tried to synthesize that I knew the synthesizer would choke on (because I knew that the design was counter-intuitive from a hardware perspective), and I got lousy results, as expected. One interesting rule of thumb in software development is that smaller code is faster. Although it's not true all of the time, statistically, if I write a function to perform a task and my code is significantly smaller than my co-worker's verion, my code will run faster. Exactly the opposite is true with chip design. The more explicit you are about the hardware you want, the better the synthesizer will understand what you want and be able to give you a good result. Remember that you are smarter than the synthesizer. Of course, telling the synthesizer that you want an adder is a bit of an abstraction over telling what gates you want for an adder, but nevertheless, when you say "a I'm sure some more experienced chip designers will see inexperience in what I'm saying, but from some of the other comments I have read, I think many generally agree with me. The bottom line is that although some languages may be better for chip design than others, good chip design comes from a chip-design way of thinking, which is completely unlike software engineering. One tip comes to mine, BTW. Many chips are embedded in systems with a CPU that will be controlling it. Don't try to put too much into the hardware. A little software can save a lot of hardware without any loss of performance or functionality.
http://www.starbridgesystems.com/cont-tech.html
I'm surprised I didn't see this at the top of the responses. These guys have, if their claims are accurrate (they are shipping hardware, supposedly to the likes of Nasa, so...), revolutionized both the FPGA development process and computer hardware architecture.
Their ideas seem to be based on the idea that a big array of FPGAs, which are reconfigured on the fly to suit a specific application at the gate level, is significantly (they claim orders of magnitude) faster than a conventional general purpose Von Neuman CPU or CPUs (even modern Athlons, etc). The frightening thing is that intuitively it makes sense to me, and if it really does work, it could change everything.
Obviously to make this work, they've developed a high-level language which compiles down to the FPGA level... They call it IIADL and/or Viva...
Looks fascinating.
-David
We're on the road to Tycho.
In June '01, Mike Butts published an independent reimplementation of the xr16 instruction set architecture, written in JHDL.
t ml
4 88
See:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.h
http://www.fpgacpu.org/log/jul01.html#010731
http://groups.yahoo.com/group/fpga-cpu/message/
was the designed of Ada (83). Ada (83) was an object based language, but not truly object oriented. Ada (95) is object oriented. It really is a nice language whereas Ada (83) isn't. It's too bad that when they finally fixed it that the US government abandonned it.
It is true that building hardware and coding software are different thought processes - to a point. Hardware is inherently parallel, and thus you must think in terms of everything happening simultaneously/in parallel.
JHDL has advantages that you attribute to both VHDL and Verilog. Because it is based on Java, it is much easier to debug than a C-based HDL. Java is also much easier syntactically than VHDL OR Verilog.
JHDL is structural. In JHDL, you describe your circuit using java classes to represent circuit components - for me very intuitive. If you want an AND gate, you instance a new AND gate.
Also, it is very easy to write parametric circuits in JHDL - i.e., an arbitrary-width adder.
JHDL currently does not have a "finished" synthesis tool, but it is currently being worked on. So in the future you will get the best of both worlds - a powerful structural description and synthesis capabilities...
Does anyone out there know if any of the PLD companies (Xilinx, Altera, etc) offer inexpensive (<$500) dev kits for personal/noncommercial use?
I've been wanting to try using PLDs in some of my projects for pretty much as long as I've known such things existed,
but the cost of the tools I've seen is prohibitive to most anyone without corporate or university backing.
C-X C-S
First, VHDL was developed as a simulation language. Later, when industry discovered that what it really wanted was an automated tool that converted an HDL to a hardware design, VHDL was adopted as an input language for that process. Large portions of the VHDL language cannot, in fact, be used when the goal is to synthesize the resulting code into hardware. So, hardware development with VHDL is actually done with a subset of VHDL, typically referred to as synthesizable VHDL.
VHDL does indeed provide a higher-level approach to developing hardware. Some relatively simple language constructs can lead to a complex hardware implementation. It is, for instance, very easy to describe a state machine in VHDL and have the synthesis tool translate that state machine into gates and flip flops.
Since VHDL was not designed as a synthesis language, the translation of a VHDL construct into a hardware construct is not well defined. Each company that markets a VHDL synthesis tools approaches the problem differently. So, a given construct synthesized by one tool might lead to a well-optimized piece of hardware, while it leads to an ugly mess when synthesized by a different tool. To get reliable results, engineers that use synthesis tools must become experts in the particular synthesis tool they use.
Another disadvantage of VHDL is that it is very difficult to produce reusable code. It provides some mechanisms that seem useful for this purpose at first, but which, with experience, turn out to fall short. As a professional FPGA application developer, I've abandoned VHDL. I typically spend much too much time fighting with the language or the synthesis translation process.
So, what to use if not VHDL? The first thing that needs to be understood about JHDL is that it does not allow you to write your application in Java and then synthesize it into hardware. JHDL provides a mechanism for doing structural hardware design. So, you're not, for instance, writing a while loop in Java and having that translated into gates. What you would have to do is describe, in terms of the interconnection of the available hardware primitives and macros, the detailed hardware structure of your while loop. JHDL does not raise the accessibility of FPGA design. You still need to be a hardware engineer. You still need to understand the low-level nature of the hardware that you're building. What JHDL does is make it easier to do those things. JDHL is a Java-based library that allows you to build hardware structures using a real computing language.
While VHDL might seem cumbersome syntactically, you will soon realize that it brings a significant readability advantage over the c-like syntax usedinverilog and to some extent java.
As for structure. All HDL's will have some method for describing structure. VHDL uses the entity as the most common hierarchial component. A entity has a well defined interface, and may use generic parameters. In addition you can use blocs for describing smaller subcomponents and configurations for describing the overall system. (One very useful propery of VHDL is that you can have multiple implementations (architectures) of an entity. A configuration is used for selecting the apropriate one)
Genericity along with generate statements make it very easy to describe very general structures. Good for reuse.
From what I gather of JHDL is that it tries to be a behavioral description language rather than an HDL. This poses a problem at synthesis as behavioral synthesis is a lot tougher and more error prone process than rtl synthesis (though improvements are beeing made)
I don't really see at first glance what this particular language might offer (though it might find a slot in dynamically reconfigurable circuits, (which is rather margial IMO)).