Slashdot Mirror

← Back to Stories (view on slashdot.org)

Intel Hyperthreading In Reality

Posted by ryuzaki0 on from the make-go-faster dept.

A reader writes: "Looks like GamePC has got the first look at Intel's new Xeon processor, which has the new super-fantastico Hyperthreading technology, which tricks your OS into thinking one CPU is two CPUs, two CPUs is four. Looks neat in theory, benchies included."

5 of 285 comments (clear)

  1. Watch out for the XBox 2 from Intel by Asterax · · Score: 0, Offtopic

    Heh, the XBox 2 is coming now instead of Microsoft, Intel will get into the Video Game action.

  2. Problems With Slashdot by wizarddc · · Score: 0, Offtopic

    I don't know where else to post this, but has anyone been experiencing problems
    with Slashdot? More specifically, cookie problem, such as not being logged in
    when you vist the site? For the past three days, I've had to log into Slashdot
    multiple times thoughout the day. I've also gotten errors on the site that force
    the cookie to be written to the screen. Is there any place where we can see/post
    bugs/bugfixes for the site? Or a thread where we can see status on the site in
    general? I enjoy reading the site too much to get fed up with small problems.

    --
    Th
  3. These machines are wonderful by Xanthos28 · · Score: 2, Offtopic

    Last friday I got my first taste of the Xeon processor. I work for a company that makes heavily optimizing OpenMP compilers, and we tend to get some of the latest hardware in short order. Last friday, I set up a machine with:

    Dual Xeon 2.0Ghz CPUs (3997 bogomips on RH7.2)
    1Ghz ram
    36Gb disk

    This machine is extremely fast. A test suite that runs in 4 hours on a dual PIII 800MHz (512MbRam) runs in about 45 minutes on this machine.

  4. Re:Hyperthreading useless on Win2K? (OT) by syzxys · · Score: 0, Offtopic

    I did. It works in C++ too. :-)

    ---
    Windows 2000/XP stable? safe? secure? 5 lines of simple C code say otherwise!
  5. How the CDC 6600 PPU worked by Huusker · · Score: 1, Offtopic
    This isn't a totally new idea, either. The first step in this direction was the peripheral processor for the CDC 6600, in the 1960s, which appeared as ten peripheral processors to the programmer. Internally, it was ten sets of registers and one ALU, doing one instruction for each machine state in turn.

    Here is how it worked. On the CDC 6600 when the CPU wanted to do I/O it would store a request packet into a magic memory address. The next virtual PPU would scoop it up and shovel the bits into the device. There was no DMA. The PPUs polled the I/O port to push each word of data. They also did most of the 'system call' functions. For example for a context switch the PPU would order the CPU to dump its registers and halt, then the PPU would swap in the new registers and order it to resume and load.

    Each PPU ran one instruction before switching. The design documents called the switching logic the 'barrel', as in the drinking song Roll Out the Barrel. The design engineers must have liked their beer :-)