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Design Your Very Own Microprocessor
LightJockey writes: "CircuitCellar has a great article on designing and building your own microprocessor using FPGAs and openly available processor designs, ranging from ARM and MIPS based to custom designs, and even a couple SPARC based chips, and also a really cool 'processor toaster,' start with a base processor design, and using a webpage to select upgraded components, it spits out the VHDL file you need to create it. Brings garage hackerdom up to a whole new level!"
I attended an IEEE meeting at my school recently, and a guy from Xilinx presented and demoed FPGAs (their brand of course) and told us why we should use FPGAs for our signal processing needs. Of course, being an SE student, there were quite a few thngs that were over my head, but of course talking about the massive paralellism clicked with me, and of course hearing that one client of theirs had OC-768 signal processing within one FPGA chip, well, that was pretty damn cool. Also, being able to design your circuits with a nice GUI interface, rather than in VHDL or Verilog or whatever, looked pretty damn cool.
"I would say that 99 per cent of what my father has written about his own life is false." - L. Ron Hubbard Jr.
Since most articles are /.ed as soon as they are posted. I think a great feature for subscribers would be a mirror to each article that is hosted on slashdot.
Hacker Media
Replace
....
'Microprocessor' with 'Operating System'
'Intel' with 'Microsoft'
'AMD' with 'Sun'
Read the above comment again. ; )
Building a chip in a fab would have to be a traditional commercial endevour. Agreed. Aren't Boeing and Airbus the only two airline manufacturers because they are subsidized and therefore others cannot compete? Cheers!
The scary thought is that the RIAA and the MPAA might try to outlaw private possession of FPGA design tools and burners for just that reason. If the "encrypted all the way to the monitor/speaker" concept ever takes hold, you'll need to build hardware to get unencrypted digital content out. And an FPGA is the only reasonable way to build one-off complex digital hardware.
I was assuming at least 0.35um.
These prices are however just for the fabrication, no?
If so you will still need to do synthesis and P&R.
Of cource your point about just dropping in a processor as beeing uninteresting is well taken. Indeed a CPU is a very inefficient piece of logic. Dropping CPUs in FPGAs seem to me as a particularly stupid thing to do.
The whole reason many want a CPU in a SoC product is that they want the flexibility to reconfigure the chip and update it's algorithms without having to fabricate a new device. On a FPGA you allready have the flexibility to update at any time at practically no cost, so on those you will want to forgo the CPU entirely and implement the algorithm completely in hardware.
Also since FPGAs generally are unable to reach high clockspeeds, the designer really need to paralellize his algorithm to achieve any kind of performance.
(We recently have done a SoC project which was to be prototyped in a FPGA which included a 16 bit single issue unpipelined RISC core. On a virtex II 3000-4 this achieved a speed of 18MHz max)
OK, you can reimplement a modern processor core in an
:)
FPGA if you really want to (I can guarentee you that
the FPGA will NEVER run anywhere near as fast as the
regular chip) or you can do what I did for our senior
design project
We used a Xilinx Spartan II to run the main board on a model helicopter control. The idea was that several sensors, including a 2 axis tilt, accelerometers, RF controller and an ultrasonic sonar could be easily integrated into the VHDL core, and then the chip would calculate 4 PWM outputs that drove the 4 motors. While the thing unfortunately didn't fly (weight problems, but hey, we're CompE's not aeros!) the board itself worked
great and the software UART outputted all sorts of fun data about what was going on.
Here's the interesting kicker: The entire system was clocked at a grand total of 1MHz (that's right folks, 1Mhz) and even that was too fast for most of the onboard operations that we internally clock divided. This thing operated all of the components completely in parallel, so there were no interrupts needed at all. The reconfigurability of the FPGA means you can quickly adapt it to solve a whole bunch of specialized problems very efficiently and quickly. This thing definitely met the criterion for a hard realtime system (motor updates within 1ms of a sensor or RF input) and it did it all
via VHDL code, no OS or any high level software needed.
Now obviously this is a very embedded solution and is not extremely flexible, but sometimes you need to step back and look at the true advantages that the hardware provides for you, and use it for something other than reimplementing someone else's CPU core, (of course, that
can be a hell of alot of fun too.... mmm... 21st Century overclocked Trash 80)
PS--> use my spam address: foxcm2000@hotmail.com and
I'll be more than happy to send you all the VHDL we used
to implement the project since I just graduated yesterday!
AntiFA: An abbreviation for Anti First Amendment.
Just because you can claim that other complex products have been created by people with fewer resources, does not invalidate the original post. The cost of entry into the software market is HUGELY less than entry into hardware. Within hardware design, there are many fields where the bar to entry is very low (simple Data Acquisition/Control interfaces come to mind) and many amateurs are selling commercial products. But most of the high-end stuff requiring expensive tools is beyond the reach of the guy in the garage. I guess my point is that, to take Linux as an example, you can write a kernel and have it be immediately useful. Heck,I've done this by writing a small preemptive RTOS kernel for my own use. But simply building, say, a pipelined arithmetic processing unit gets you nothing without the rest of the CPU around it.
There are many areas in electronics where those of us struggling in the basement can build high-performance equipment, but CPU design is not one of them.
Apples and onions, dude.
Take a few more advanced architecture classes.
ISA's are mostly irrelevant in terms of performance potential (except for IA-64 which I will get to). Both AMD and Intel devote a (small) portion of their transistor budget to dynamically convert the CISC instructions into RISC-like "micro-ops". Thus the actual execution core of the AMD K7 and Intel P6 micro-architectures are very similar to say the MIPS R10000 core. Now if Intel and AMD had a decent ISA to begin with, they could devote those transistors (used to convert CISC to RISC) to things like bigger caches. Thus the performance penalty of using a lousy ISA is really not that much as evident by the success of Intel and AMD in raw computational power.
Your comment about "RISC chips are really not all that complex" is extremely ignorant and uneducated. Please tell me again that the MIPS R12000 core is "not all that complex" after studying about superscaler speculative out-of-order execution.
The IA-64 ISA really is different because it takes a radical approach to achieving instruction-level parallelism. It is very VLIW-like and contains many advanced features like "poison bits", register windows (not SPARC windows), software pipeline support, etc. Thus the parallelism is discovered by the compiler and can be expressed to the architecture unlike RISC and CISC ISAs which rely on the hardware to discover and provide parallelism (through OOO execution).
See the "links" page in the "Java Optimized Processor" site: http://www.jopdesign.com/
I am kinda late in reply -- so no karma for me -- but for the record: i wonder how they test these suckers as they come off the toaster (haha, toaster)?
usually any chip would require a custom program to be run on a (very expensive, i might add) tester that will test the thing; writing the program is not cheap, i wonder how they factor in those costs? I wonder if anybody beside me on slashdot thought of this as a serious challenge?
My life in the land of the rising sun.