Nanoimprint Lithography

An anonymous submitter writes "According to BBC News, researchers at Princeton have developed a die-stamp method for chip fabs. The Princeton site claims they've got to 10nm already. The professor in charge has told BBC News Online that they're '20 years ahead of Moore's Law.' Dubious claims aside, it looks like a handy way to bring down prices even if it doesn't improve ultimate top speed."

Comments

Important Issue

[imta11]

How do they make the ultra small quartz die to burn the patterns? Grow it perhaps?

Re:Important Issue

[YourGarbageMan]

The same way they make phase shift masks for optical lithography. They use an ebeam writer to expose a pattern onto a photoresist layer on a quartz substrate. Then they develop the resist, etch away the quartz and then strip the resist. Ebeam writers have very high resolution and printing patterns of this size is not a problem.

Great for stamping holes. How about traces?

[Goldenhawk]

The two links gush with claims but provide little evidence of its utility. The only demonstration shown there demonstrates making holes in substrate, or leaving dots of material. It does not show making any traces. I'd wait to be impressed until I see something beyond a row of dots.

But how do you make the mold?

[joshv]

This sounds great, but how do they make the mold, what kind of wear and tear is the mold subject to? My guess is that one of these 'nano-imprint' molds is not going to last all that long.

I am assuming they are relying on something like electron beam lithography to create the imprint mold, certainly this would be a cost/time improvement over direct e-beam litho, but it all depends on longevity of the molds.

-josh

Environmentally friendly!

[pokeyburro]

Take note of that third section: no nasty chemicals, they claim. If their claim holds, a company using this tech could make a lot of political capital from it.

Natural questions arise: just how dirty is the current process? Will the details of the method really prove to be as clean as they say?

Re:Really?

[hagardtroll]

Moore's Law is just based on a different commercial corrollary(sp?) That is, hardware manufacturers will improve electronics features/performance at the rate that will maxmize profit for them. We all know Intel had 2Ghz chips 6 years ago, but they just increase the speed incrementally until we all upgrade. Then they release the next round of chips. In all seriousness. I knew a lady who worked for DEC and she said they purpsosefully put NOPs in the microcode in their Vax, so they could sell a "Faster" version later. They just removed the NOPs.

Crystal structure

[fava]

The article states that the silicon wafer is melted briefly by a laser. Considering that the silicon wafers are actual single crystals, wont the melting and re-solidification of the silicon alter the properties of the wafer.

So instead of having a single crystal we could end up with many small crystals aligned along the features that we are creating. I am not sure how much the creation of semiconductors is dependant on having a single crystal, but if it is dependant then this new technique may not be that useful after all.

What about electron-migration?

[Elledan]

Isn't this one of the main problems chip-manufacturers have to deal with now that individual transistors are becoming so small?

I'd imagine that the electron-migration with 10 nm transistors is pretty bad, not to mention the inferference between individual traces.

I could be horribly wrong, though. Anyone wants to hit me with a clue-stick? :)

A little math

[quintessent]

The observation that the computing power which can be incorporated in a given sized piece of silicon doubles roughly every 18 months was put forward by the head of Intel, Gordon Moore, in 1965. - BBC News.

We're probably 20 years ahead of the curve, - Professor Chou.

Seems a little exaggerated. Let's look at the numbers.

The article says they're 100x as dense (in area) as current technology.

if 2^7=128, then technology needs to double fewer than 7 times.

7 * 1.5 years = 10.5 years, far fewer than the claimed 20 years.

And this technology is still vaporware, so even 10.5 years is exaggerated.

Sounds cool, though. It would be nice if this really worked.

Particles?

[mactom]

We do standard old fashioned i-line lithography (0.35m), old fashioned proximity lithography (1.5 m), decent laser direct write lithography (0.8 m) and top of the line e-beam direct write lithography ( 100 nm). The smaller the feature size gets, the more problems do we have with particles on the substrate, causing defects. Proximity lithography is suffering from defects caused by particles that form from the direct contact between the mask and the substrate. Thinking of an embossing method for resist patterning gives me a bad feeling about generated particles adhering to the stamp-mask. Especially at 10 nm feature size. Very questionable. Also, the wall angle of the patterned resist seems far off of the desired 90 degrees. The etch behaviour of such shallow slopes is difficult to control and leads to variance in etched feature size. This is an interesting lab experiment, but I cannot imagine it for high volume chip production at all.