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Printing Chips
batty writes :"Nature has this article about a process that uses a quartz die and a laser to mechanically print features onto chips instead of photo-etching them. The article mentions engraving a silicon wafer with features only 10 nanometres in size, as opposed to 130 nanometres using photlithography, and the process is quicker, simpler, and more environmentally friendly than current processes. Which is nice."
instead of photo-etching them
...
With the current technology, the photons are not used directly to etch the silicon, but it is used to act on a photo-sensitive compound, which will then protect (or not) the silicon against acid etching, ion implant,
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... four days ago. But thanks for the link to the Nature article.
The author of this article from Princeton was reported in the BBC as saying he thinks he can outstrip Moores Law with this new technology!
Its one damn thing before another. (Dick Bird 1999)
"It gives an unsurpassed combination of speed and resolution and isn't limited by physical laws."
Also, the tecnique will be used for a myriad of other things, including spaceships made entirely of silicon, allowing them to be freed from laws of gravity and friction.
When you hear about CPUs... they quote it in microns.. So instead of 0.13 microns (latest intel P4), it can acheive 0.01 micron. But will the circuitry actually WORK at that size? I've heard 0.01 micron is about the limit of what semiconductors will work at until quantum effects step in and ruin the party ;-)
The whole process takes just 250 nanoseconds - nearly a million times faster than the blink of an eye.
Thanks for the meaningful comparison.
In other news, computers can add 2+2 three trillion times faster than you can commute to work. More at 11.
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No... this talks about using fricken' "LASER BEAMS"... ;-)
sheesh...
How long does a CD mold last?
Really, it should last a fair bit of time, quartz is durable. Rather hard, fairly high melting point points to it being ideal for this use.
Good grief, study some EE instead of spouting off.
Silicon is used to make the TRANSISTORS. This is because it is easy to implant boron etc. into the silicon for making the wells in the transistor. This process (if manufacturable in high volume) will be useful for making the TRANSISTORS. You still have to connect them. What are you going to do, deposit silicon on top of the wafer, now, to make another "mask"? Then melt the silicon and pour in metal on top of that or something? If you've figured out how to do that the combined might of the semiconductor industry wants to pay you a lot of money!
No, you have to deposit various layers of metal and dielectric to connect the transistors. Many ICs have up to 7 or 8 layers of metalization, which means depositing the ILD, putting in interconnects, and depositing the metal (think "wires"). Currently the only way to do this is through photo masking followed by some deposition process.
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This is really interesting, an exact copy of the comment I posted to this same story four days ago...
Enterprising young ACs.
-josh
I believe they also talked about using this process in combination with a polymer based photoresist. The idea being you coat the surface with the photoresist, plop the die down on top. Where the die makes contact it pushes away the resist. A flash of UV cures the polymer - et voila, ready for etching or deposition.
-josh
You have a number of implicit assumptions in your comment which I would like to query. As well as the /. article, I have read the The Economists take on the same research.
Point 1 - they are not talking about a single-die stamper. Actually they were talking about a whole-wafer stamper, created by e-beam lithography, If, as you suggest, a single stamper is good for only 500 stamps, this gives a 500:1 power boost to e-beam - good going.
Point 2, the stamping is not purely mechanical. A laser beam at a frequency at which the quartz stamper is transparent but the silicon isn't is shone through the stamper. This softens the silicon, so the stamper presses into it. No photoresist, and far less mechanical wear on the stamper. Quartz is pretty damned hard stuff, whereas softened silicon is (I guess) not - so I would guess a lifetime in the thousands or tens of thousands for the stamper, not hundreds.
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Yeah, I can see where this'd be useful.
Actually, I was gonna cut off my comment ther, butt I figgered I cood right mor abowt thiz. So heer it iz. Printin' chips cood bring the price down and allow finer resolution or whatever, making it possible to put a million billion tranziztorz on a dam chip, making it possible to make chips so complicated that a program to printf "hello world" will be like a thousand gigabytes, because there'd be like 999 gigabytes of setup code to get all the transistors pointing in the right direction or something, and then like a gigabyte of code to actually do the work, and the whole damn thing'll get executed in like five days or something. It'll have like a million billion exahertz internal clock, so they'll sell it by that number and people will buy, but in reality, they'll've broken each operation into like 500,000,000,000,000,000,000,000,000 separate stages in the processor, so when it comes down to it, it'll take up like a trillion gigawatt-hours of electricity to power this processor for like a picosecond, and then the whole damn grid will meltdown, leaving us in the stoneage or something. Ooooooooooooooh well.
Yeah, you should've let me stop at that first sentence where I originally planned to stop, but, you know, whatever.
Also, let's say that the stamper can do 1 stamp per minute (aggressive, but ya gotta make some assumptions). How do you determine when the first little imprinter point snaps off, and every subsequent stamp creates a dead die. If it happens during the first several hundred wafers patterned, and the stamper isn't changed for thousands of stamps, there's going to be an awful lot of non-yielding die at end of line. That's a real bummer, because nobody buys the chips that fail sort/etest for anything more challenging than pretty keychains/ornaments.
Another problem is going to be that the surface of a wafer is *not* flat. Run a wafer through a diffusion furnace, and it warps like an album left in the sun (ok, so I'm dating myself... but the analogy is valid). Let's assume that the wafer bows up at the edges, relative to the center. If you try to press the entire wafer at once, you are going to get excessive pressures at the edges, while the center of the wafer isn't yet touched by the stamper. As a result, the center of the wafer isn't going to get any pattern, and so the center of the wafer won't yield usable die. Bummer.
Another issue is that *all* wafers end up with particles on the surface, be it aluminum, stainless steel, tantalum, or just plain old dust. What happens to the little imprinter fingers when you try to press them into a hunk of steel? I'll give you a hint, it'll be like holding your fingers out straight and punching a bowling ball... your fingers are gonna break. How well are your fingers going to be at pressing anything after that? On the wafer scale, any stamper which hits a die that has a surface defect will result in that die being defective on all subsequent pressings. More keychain ornaments, but less working chips and much less profitable.
In closing, let's consider one other little issue. In patterning, the goal is to have the sidewalls as nearly perpendicular to the surface as possible. A cross section view of a line should look like a skyscraper, with vertical sides, and not like a pyramid/trapezoid. In order to stamp and be able to extract the stamper from the imprinted surface without ripping off teeth, the impresser has to be tapered to minimize friction effects. Etchers and implanters really don't do well with tapered sidewalls on the pattern... you lose resolution of the resultant structures/implants.
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Nature's article stated that a laser was used to 'liquify' silicon and then the quartz mask was pressed into the resulting mush. This doesn't make sense because (a) heat is something you dont want when doing fine patterning - thermal expansion tends to cause everything to shift by microns, and you want to work with nanometers. (b) Melting silicon and then quickly re-cooling it tends to destroy the crystal structure which is needed for semiconductors to work. Making a single Si crystal requires long, SLOW cooling. (c) Even if the previous items could be overcome, so what? Pressing a pattern into liquid Si and then cooling it gives you lumpy silicon - not a transistor. Transistors are made by putting small amounts of impurities (Phosphorus and Arsenic mostly) into the Si which changes the conductivity and the dominant charge carriers.
Sooo... Assuming that Nature really boned this one up, here's how the Scientific American version works: A thin layer of polymer (like a photoresist) is spread over the wafer, then the mask is carefuly aligned to any existing structures and placed in contact with the wafer/polymer combo. The laser is then used to cause a photochemical reaction that hardens the polymer in places where it isn't protected by the mask. The remaining soft polymer is then removed (I'm guessing there's a solvent step here - so much for the no chemical use idea) and the result is the pattern of whatever you're trying to make left in the hardened polymer. From here, you can etch, implant, or whatever other normal Si processing step you want. The main difference seems to be that the contact mask in the new process and the thin polymer layers give a higher resolution.
If anyone has more specific info or a link to a technical paper, please post it. Right now it appears that we have two major science magazines in conflict, and from my experience (I once had to build a mask generator in grad school - amazing what you can do with LabView and some old photography equipment) the SciAm version makes a heck of a lot more sense.
65nm .40nm CMOS process and apparently we're only a few years from that. .5 micron technology. When Taiwan is absolutely positive there are no more decent profits in it, they'll hand it to the Mainland and say, OK, let's be friends now. This process started several years ago already with TSMC's relocation of a few fabs across the strait and is probably going to conclude in the next several years with both TSMC and UMC moving all operations to Mainland China. Prices will drop to level unthinkable to most Americans --two or three bucks for multi GHz CPUs-- but high end performance will become an elite game with overpriced specialty chips unsuited for the consumer market still being made in the US and Europe.
UMC has already started a joint venture with a German firn in Sinagapore at 65nm. Production is set to start in '04 or '05. Apparently people within IBM think this is getting towards the end of the line on CMOS shrinking for performance enhancement although further shrinkage would enable more transistors in a smaller area they wouldn't necessarily be faster. If you don't like to hear bad news, Intel will be happy to cheer you up. They say THz desktop chips are no problem and everybody is goingto want one, but I think they have a good reason to be deceptively optomistic. I tend to believe IBM over Intel in this debate and although they're also optomistic for gains over a long time scale, but they're pretty gloomy in near term prognostications. I seem to have read several places where they say yeah chips could be much faster, but not both cheaper and faster any time soon once we get past the
Personally, I think this is about it. Taiwan started moving everything to China several years ago and anybody who thinks the technology is going to be highly refined by transferring it to the Mainland has obviously never been to the two countries in question. Mainland is currently riding around on training wheels making chips using
Regjected because the defect rate was too large. What has changed?