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Fin-Fet Transistors on the Horizon
MORTAR_COMBAT! writes "According to this 9 September News.com article, IBM scientists have "manufactured a working static RAM chip out of so-called Fin-Fet transistors, which feature two gates, rather than a single one, for conducting electricity". What does this mean for us? 50 percent performance increases, due to increased throughput of electricity, and 50 percent less power usage, due to decreased electrical leakage. Longer battery life for laptops, lower power bills for server farms. Moore's law lives on. More pretty pictures here."
Link
The first one is very good. It explains the problems with conventional scaling methods then presents the solution to the Gordian knot, the FinFet. Found by searching IBM chips (It is on my information resources list)
Maintaining the benefits of CMOS scaling when scaling bogs down
Process requirements for continued scaling of CMOS--the need and prospects for atomic-level manipulation
It's not quite a Melded Darlington, but it certainly reminds me of a Darlington pair.
A Darlington is two transistors tied together where emitter of one goes straight into the base of the other. This basically sharpens the gain, but you pay a price in speed. Nonetheless, Darlingtons are used, as well as Photo-Darlingtons.
I had just about forgotten everything about transitors from my EE days until I picked up robotics. Software really isoltated you from how things really work.
New transitor designs are a dime a dozen. For instance the tunnel diode. (A diode is the most basic semi-conductor, a transitor is basically two diodes.
Pick up electronics as a hobby. I urge you EE's out there that like me are writing business software. It's very rewarding.
The inversion layer forms on the sides of the fin and the conduction occurs along the fin. Actually, at these dimensions it is debatable that you may have volume inversion of the fin. The source/drain contacts occur at the ends of the fins. A top-down drawing/SEM would have helped.
Ok, now I understand. I was much confused by all the press writing "two gate" device. Every rational NAND/NOR gate made in a MOS process is made with 2 gates. A 4 input device would have 4 gates.
The big advantage of the FinFet device is rather than being an embedded surface device with the gate on top of the channel which is embedded in the substrate, the FinFet uses a channel elevated out of the substrate so the gate wraps three sides of the channel. The papers report access to the top and bottom of the channel as "two gates" it is really a three side wrapping of the source-drain channel which is raised out of the substrate.
The big advantage is that for a given gate voltage the penetration into the channel in blocking carriers is only so far. With the gate on both(3) sides of the channel the penetration effectiveness for a given voltage is greatly increased.
Actually the performance benefit from double-gate is minimal. The approximate delay associated with switching a capacitor is CV/I, where C is the capacitance of the gate, V is the source voltage, and I is the on current of the device. Double-gate gives you double (or slightly more) the current, at the expense of twice the capacitance. You don't really gain much at the same gate length. The real advantage is scaling. You can make shorter double-gate FETs, and gain the kind of performance you're used to from following Moore's "Law".
- From the post: "... and 50 percent less power usage."
- From the web site: "... new type of transistor which reduces power consumption by 20 - 25%."
Somewhere along the way, that thing got twice as efficient! Amazing design.Too big to fail? Does that make me to small to succeed?