Fin-Fet Transistors on the Horizon

MORTAR_COMBAT! writes "According to this 9 September News.com article, IBM scientists have "manufactured a working static RAM chip out of so-called Fin-Fet transistors, which feature two gates, rather than a single one, for conducting electricity". What does this mean for us? 50 percent performance increases, due to increased throughput of electricity, and 50 percent less power usage, due to decreased electrical leakage. Longer battery life for laptops, lower power bills for server farms. Moore's law lives on. More pretty pictures here."

Comments

IBM reference papers (not too technical)

[RichMan]

The first one is very good. It explains the problems with conventional scaling methods then presents the solution to the Gordian knot, the FinFet. Found by searching IBM chips (It is on my information resources list)

Maintaining the benefits of CMOS scaling when scaling bogs down


Process requirements for continued scaling of CMOS--the need and prospects for atomic-level manipulation

2 gates, NO, elevated channel wrapped by a gate.

[RichMan]

Ok, now I understand. I was much confused by all the press writing "two gate" device. Every rational NAND/NOR gate made in a MOS process is made with 2 gates. A 4 input device would have 4 gates.

The big advantage of the FinFet device is rather than being an embedded surface device with the gate on top of the channel which is embedded in the substrate, the FinFet uses a channel elevated out of the substrate so the gate wraps three sides of the channel. The papers report access to the top and bottom of the channel as "two gates" it is really a three side wrapping of the source-drain channel which is raised out of the substrate.

The big advantage is that for a given gate voltage the penetration into the channel in blocking carriers is only so far. With the gate on both(3) sides of the channel the penetration effectiveness for a given voltage is greatly increased.

More Slashdot hype

[trenton]

And the hype lives on! Compare and contrast:

• From the post: "... and 50 percent less power usage."
• From the web site: "... new type of transistor which reduces power consumption by 20 - 25%."

Somewhere along the way, that thing got twice as efficient! Amazing design.